Inventor
CHAO LI-CHIH
TW20 patents
⚠️ This page may combine multiple inventors who share the name “CHAO LI-CHIH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
TAIWAN SEMICONDUCTOR MFG
19 patentsUS6743732B1Jun 1, 2004
Organic low K dielectric etch with NH3 chemistry
TAIWAN SEMICONDUCTOR MFG249 citations99
US6165880ADec 26, 2000
Double spacer technology for making self-aligned contacts (SAC) on semiconductor integrated circuits
TAIWAN SEMICONDUCTOR MFG186 citations99
US6720256B1Apr 13, 2004
Method of dual damascene patterning
TAIWAN SEMICONDUCTOR MFG78 citations98
US6323121B1Nov 27, 2001
Fully dry post-via-etch cleaning method for a damascene process
TAIWAN SEMICONDUCTOR MFG206 citations98
US6211061B1Apr 3, 2001
Dual damascene process for carbon-based low-K materials
TAIWAN SEMICONDUCTOR MFG91 citations97
US6063711AMay 16, 2000
High selectivity etching stop layer for damascene process
TAIWAN SEMICONDUCTOR MFG47 citations93
US5872063AFeb 16, 1999
Self-aligned contact structures using high selectivity etching
TAIWAN SEMICONDUCTOR MFG25 citations93
US6797630B1Sep 28, 2004
Partial via hard mask open on low-k dual damascene etch with dual hard mask (DHM) approach
TAIWAN SEMICONDUCTOR MFG20 citations92
US6495469B1Dec 17, 2002
High selectivity, low etch depth micro-loading process for non stop layer damascene etch
TAIWAN SEMICONDUCTOR MFG20 citations92
US6458650B1Oct 1, 2002
CU second electrode process with in situ ashing and oxidation process
TAIWAN SEMICONDUCTOR MFG34 citations92
US6429119B1Aug 6, 2002
Dual damascene process to reduce etch barrier thickness
TAIWAN SEMICONDUCTOR MFG36 citations92
US6376366B1Apr 23, 2002
Partial hard mask open process for hard mask dual damascene etch
TAIWAN SEMICONDUCTOR MFG49 citations92
US6457477B1Oct 1, 2002
Method of cleaning a copper/porous low-k dual damascene etch
TAIWAN SEMICONDUCTOR MFG31 citations89
US6172411B1Jan 9, 2001
Self-aligned contact structures using high selectivity etching
TAIWAN SEMICONDUCTOR MFG7 citations74
US6140218AOct 31, 2000
Method for fabricating a T-shaped hard mask/conductor profile to improve self-aligned contact isolation
TAIWAN SEMICONDUCTOR MFG12 citations74
US6107206AAug 22, 2000
Method for etching shallow trenches in a semiconductor body
TAIWAN SEMICONDUCTOR MFG6 citations63
US7253112B2Aug 7, 2007
Dual damascene process
TAIWAN SEMICONDUCTOR MFG5 citations61
US6727183B1Apr 27, 2004
Prevention of spiking in ultra low dielectric constant material
TAIWAN SEMICONDUCTOR MFG2 citations60
US6184149B1Feb 6, 2001
Method for monitoring self-aligned contact etching
TAIWAN SEMICONDUCTOR MFG1 citations52