Inventor
MARISETTY SURESH
US12 patents
⚠️ This page may combine multiple inventors who share the name “MARISETTY SURESH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
11 patentsUS7546487B2Jun 9, 2009
OS and firmware coordinated error handling using transparent firmware intercept and firmware services
INTEL CORP85 citations97
US6754828B1Jun 22, 2004
Algorithm for non-volatile memory updates
INTEL CORP71 citations97
US6675324B2Jan 6, 2004
Rendezvous of processors with OS coordination
INTEL CORP55 citations95
US7117396B2Oct 3, 2006
Scalable CPU error recorder
INTEL CORP26 citations92
US5574868ANov 12, 1996
Bus grant prediction technique for a split transaction bus in a multiprocessor computer system
INTEL CORP34 citations92
US7904751B2Mar 8, 2011
System abstraction layer, processor abstraction layer, and operating system error handling
INTEL CORP16 citations91
US7308610B2Dec 11, 2007
Method and apparatus for handling errors in a processing system
INTEL CORP23 citations89
US7721148B2May 18, 2010
Method and apparatus for redirection of machine check interrupts in multithreaded systems
INTEL CORP17 citations82
US7533300B2May 12, 2009
Configurable error handling apparatus and methods to operate the same
INTEL CORP8 citations79
US7353433B2Apr 1, 2008
Poisoned error signaling for proactive OS recovery
INTEL CORP5 citations60
US7502959B2Mar 10, 2009
Error correction apparatus, systems, and methods
INTEL CORP0 citations51