P

Inventor

LIN HORNG-CHIH

TW21 patents
⚠️ This page may combine multiple inventors who share the name “LIN HORNG-CHIH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NAT SCIENCE COUNCIL

7 patents
US5783479AJul 21, 1998

Structure and method for manufacturing improved FETs having T-shaped gates

NAT SCIENCE COUNCIL103 citations98
US5658806AAug 19, 1997

Method for fabricating thin-film transistor with bottom-gate or dual-gate configuration

NAT SCIENCE COUNCIL164 citations97
US5827768AOct 27, 1998

Method for manufacturing an MOS transistor having a self-aligned and planarized raised source/drain structure

NAT SCIENCE COUNCIL25 citations92
US6432786B2Aug 13, 2002

Method of forming a gate oxide layer with an improved ability to resist the process damage

NAT SCIENCE COUNCIL16 citations84
US6495432B2Dec 17, 2002

Method of improving a dual gate CMOS transistor to resist the boron-penetrating effect

NAT SCIENCE COUNCIL2 citations63
US5913123AJun 15, 1999

Manufacturing method for deep-submicron P-type metal-oxide semiconductor shallow junction

NAT SCIENCE COUNCIL6 citations55
US6232206B1May 15, 2001

Method for forming electrostatic discharge (ESD) protection transistors

NAT SCIENCE COUNCIL1 citations52

UNIV NAT CHIAO TUNG

3 patents
US7723789B2May 25, 2010

Nonvolatile memory device with nanowire channel and method for fabricating the same

UNIV NAT CHIAO TUNG66 citations91
US8932916B2Jan 13, 2015

Method for fabricating thin-film transistor

UNIV NAT CHIAO TUNG3 citations54
US7977755B2Jul 12, 2011

Suspended nanochannel transistor structure and method for fabricating the same

UNIV NAT CHIAO TUNG1 citations42

NAT SCIENCE COUNCIL REPUBLIC CHINA

2 patents
US5998246ADec 7, 1999

Self-aligned manufacturing method of a thin film transistor for forming a single-crystal bottom-gate and an offset drain

NAT SCIENCE COUNCIL REPUBLIC CHINA14 citations74
US5714398AFeb 3, 1998

Self-aligned tungsten strapped source/drain and gate technology for deep submicron CMOS

NAT SCIENCE COUNCIL REPUBLIC CHINA13 citations72

TAIWAN SEMICONDUCTOR MFG CO LTD

2 patents
US9653552B2May 16, 2017

Body-tied, strained-channel multi-gate device and methods

TAIWAN SEMICONDUCTOR MFG CO LTD2 citations72
US9406800B2Aug 2, 2016

Body-tied, strained-channel multi-gate device and methods of manufacturing same

TAIWAN SEMICONDUCTOR MFG CO LTD2 citations62

IND TECH RES INST

2 patents
US7504694B2Mar 17, 2009

Structure of semiconductor device

IND TECH RES INST2 citations63
US7972912B2Jul 5, 2011

Method of fabricating semiconductor device

IND TECH RES INST0 citations52

(unassigned)

1 patent
US6667508B2Dec 23, 2003

Nonvolatile memory having a split gate

17 citations84

TAIWAN SEMICONDUCTOR MFG

1 patent
US9214554B2Dec 15, 2015

Body-tied, strained-channel multi-gate device and methods of manufacturing same

TAIWAN SEMICONDUCTOR MFG2 citations62

UNIV NATIONAL CHIAO TUNG

1 patent
US11257845B2Feb 22, 2022

Radio frequency integrated circuit having relatively small circuit area and method of fabricating the same

UNIV NATIONAL CHIAO TUNG0 citations61

S M SZE

1 patent
US6555424B2Apr 29, 2003

Thin film transistor with sub-gates and schottky source/drain and a manufacturing method of the same

S M SZE4 citations60

LIN HONG-NIEN

1 patent
US8946811B2Feb 3, 2015

Body-tied, strained-channel multi-gate device and methods of manufacturing same

LIN HONG-NIEN2 citations56