Inventor

HUANG TIAO-YUAN

TW35 patents

⚠️ This page may combine multiple inventors who share the name “HUANG TIAO-YUAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HUANG TIAO-YUAN

VLSI TECHNOLOGY INC

Forming a MOS transistor with a recessed channel

Method of making CMOS output buffer with enhanced ESD resistance

Method for making an integrated circuit structure

CMOS output buffer with enhanced ESD resistance

Semiconductor-on-insulator integrated circuit with selectively thinned channel region

Differential treatment to selectively avoid silicide formation on ESD I/O transistors in a salicide process

SRAM memory cell with tri-level local interconnect

Method for selective salicidation of source/drain regions of a transistor

CMOS input buffer with NMOS gate coupled to VSS through undoped gate poly resistor

Multi-finger input buffer with transistor gates capacitively coupled to ground

Asymmetric electro-static discharge transistors for increased electro-static discharge hardness

CMOS input buffer with NMOS gate coupled to Vss through undoped gate poly resistor

XEROX CORP

Double implanted LDD transistor self-aligned with gate

Method for fabricating double implanted LDD transistor self-aligned with gate

Formation of large grain polycrystalline films

Method of fabrication a thin film SOI CMOS device

Simultaneously deposited thin film CMOS TFTs and their method of fabrication

Intra-gate offset high voltage thin film transistor with misalignment immunity and method of its fabrication

Intra-gate offset high voltage thin film transistor with misalignment immunity

Thin film varactors

NAT SCIENCE COUNCIL

Method for simultaneously forming local interconnect with silicided elevated source/drain MOSFET&#39;s

Structure and method for manufacturing improved FETs having T-shaped gates

Test structure for monitoring overetching of silicide during contact opening

Method for manufacturing an MOS transistor having a self-aligned and planarized raised source/drain structure

Method of forming a gate oxide layer with an improved ability to resist the process damage

Method of improving a dual gate CMOS transistor to resist the boron-penetrating effect

Method for forming electrostatic discharge (ESD) protection transistors

(unassigned)

Single-electron transistor and fabrication method thereof

Nonvolatile memory having a split gate

TAIWAN SEMICONDUCTOR MFG CO LTD

Body-tied, strained-channel multi-gate device and methods

Body-tied, strained-channel multi-gate device and methods of manufacturing same

NAT SCIENCE COUNCIL REPUBLIC CHINA

Self-aligned manufacturing method of a thin film transistor for forming a single-crystal bottom-gate and an offset drain

TAIWAN SEMICONDUCTOR MFG

Body-tied, strained-channel multi-gate device and methods of manufacturing same

S M SZE

Thin film transistor with sub-gates and schottky source/drain and a manufacturing method of the same

LIN HONG-NIEN

Body-tied, strained-channel multi-gate device and methods of manufacturing same

Method for simultaneously forming local interconnect with silicided elevated source/drain MOSFET's