Inventor

ZEJDA JINDRICH

US37 patents

⚠️ This page may combine multiple inventors who share the name “ZEJDA JINDRICH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ZEJDA JINDRICH

AMAZON TECH INC

Allocation and placement of resources for network computation

Static memory allocation for neural network inference

Time-based memory allocation for neural network inference

Performance debug for networks

Performing hardware operator fusion

Compile-time scheduling

Synchronization of computation engines with non-blocking instructions

Synchronization of concurrent computation engines

Synchronization of concurrent computation engines

Neural network operation reordering for parallel execution

Synchronization of concurrent computation engines

Fast context switching for computational networks

Arithmetic-intensity based load cloning

Neural network operation reordering for parallel execution

Performing hardware operator fusion

Neural network layer-by-layer debugging

Hierarchical partitioning of operators

XILINX INC

Data format suitable for fast massively parallel general matrix multiplication in a programmable IC

Software-defined memory bandwidth reduction by hierarchical stream buffering for general matrix multiplication in a programmable IC

Re-targetable interface for data exchange between heterogeneous systems and accelerator abstraction into software instructions

Sparse matrix processing circuitry

Software-driven design optimization for fixed-point multiply-accumulate circuitry

Software-driven design optimization for mapping between floating-point and fixed-point multiply accumulators

Software-defined buffer/transposer for general matrix multiplication in a programmable IC

Representation of complex timing characteristics of startpoint-endpoint pairs in a circuit design

Software defined neural network layer pipelining

Neural network processing system having host controlled kernel acclerators

Host-directed multi-layer neural network processing via per-layer work requests

Image preprocessing for generalized image processing

Multi-layer neural network processing by a neural network accelerator using host communicated merged weights and a package of per-layer instructions

Static block scheduling in massively parallel software defined hardware systems

Machine learning runtime library for neural network acceleration

SYNOPSYS INC

Method and apparatus for characterizing the propagation of noise through a cell in an integrated circuit

Distorted waveform propagation and crosstalk delay analysis using multiple cell models

Method and apparatus for detecting and analyzing the propagation of noise through an integrated circuit

ZEJDA JINDRICH

Multiple-power-domain static timing analysis

Integrated single spice deck sensitization for gate level tools