Inventor

BRONNER GARY B

US73 patents

⚠️ This page may combine multiple inventors who share the name “BRONNER GARY B”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BRONNER GARY B

IBM

Process for fabrication of FinFETs

Silicon-on-insulator vertical array device trench capacitor DRAM

DRAM cell with grooved transfer device

Fabrication process and structure for a contacted-body silicon-on-insulator dynamic random access memory

Method for interconnection between transfer devices and storage capacitors in memory cells and device formed thereby

Silicon-on-insulator vertical array DRAM cell with self-aligned buried strap

SOI DRAM with field-shield isolation and body contact

Self-aligned buried strap for trench type DRAM cells

Single sided buried strap

Method for providing dual work function doping and protective insulating cap

Method for making a DRAM cell with grooved transfer device

Self-aligned contact wiring process for SI devices

Oxide strip that improves planarity

Method of forming double well substrate plate trench DRAM cell array

Double well substrate plate trench DRAM cell array

High performance vertical bipolar transistor structure via self-aligning processing techniques

Out of the box vertical transistor for eDRAM on SOI

Raised STI process for multiple gate ox and sidewall protection on strained Si/SGOI structure with elevated source/drain

Out of the box vertical transistor for eDRAM on SOI

6F2 Trench EDRAM cell with double-gated vertical MOSFET and self-aligned STI

Static self-refreshing DRAM structure and operating mode

Storage-capacitor electrode and interconnect

Self-aligned damascene interconnect

Method for simultaneously forming a storage-capacitor electrode and interconnect

Process for fabricating two different gate dielectric thicknesses using a polysilicon mask and chemical mechanical polishing (CMP) planarization

Salicide device with borderless contact

Method for simultaneously forming a storage-capacitor electrode and interconnect

Method of forming a buried strap in a DRAM

SOI DRAM with field-shield isolation

Word line driver circuit for dynamic random access memories

DRAM having offset vertical transistors and method

Process for 4F2 STC cell having vertical MOSFET and buried-bitline conductor structure

Slotted damascene lines for low resistive wiring lines for integrated circuit

Low resistance fill for deep trench capacitor

Method for making DRAM capacitor strap

Non-random sub-lithography vertical stack capacitor

Method for fabricating silicon-on-insulator structures

Integration scheme enhancing deep trench capacitance in semiconductor integrated circuit devices

Method of fabricating vertical body-contacted SOI transistor

Raised STI process for multiple gate ox and sidewall protection on strained Si/SGOI sructure with elevated source/drain

Method for fabricating 6F2 trench DRAM cell with double-gated vertical MOSFET and self-aligned STI

Formulation of multiple gate oxides thicknesses without exposing gate oxide or silicon surface to photoresist

Spatially offset deep trenches for high density DRAMS

RAMBUS INC

Integrated circuit heating to effect in-situ annealing

Thermal anneal using word-line heating element

Pulse control for nonvolatile memory

INFINEON TECHNOLOGIES CORP

Single sided buried strap

KELLAM MARK D

Three-dimensional memory array stacking structure

TOSHIBA KK

Method of making a semiconductor memory device having a buried plate electrode

BRONNER GARY B

Repairing defects in a nonvolatile semiconductor memory device utilizing a heating element