Inventor

ECONOMIKOS LAERTIS

US109 patents

⚠️ This page may combine multiple inventors who share the name “ECONOMIKOS LAERTIS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ECONOMIKOS LAERTIS

IBM

Directional CVD process with optimized etchback

Structure and method for producing low leakage isolation devices

Filling of high aspect ratio trench isolation

Germanium or silicon-germanium deep trench fill by melt-flow process

Method for in-situ formation of bottle shaped trench by gas phase etching

High aspect ratio deep trench capacitor having void-free fill

Slurry-less chemical-mechanical polishing

Method to increase removal rate of oxide using fixed-abrasive

Thin film wiring scheme utilizing inter-chip site surface wiring

Slurry-less chemical-mechanical polishing

Punched slug removal system

Hermetic sealing of a substrate of high thermal conductivity using an interposer of low thermal conductivity

Structure and a method for repairing electrical lines

Method of forming a buried bitline in a vertical DRAM device

Integration scheme enhancing deep trench capacitance in semiconductor integrated circuit devices

Apparatus for providing solder interconnections to semiconductor and electronic packaging devices

Punch apparatus with improved slug removal efficiency

Filling high aspect ratio isolation structures with polysilazane based material

Hermetic sealing of a substrate of high thermal conductivity using an interposer of low thermal conductivity

Selective addition of a solder ball to an array of solder balls

Low temperature diffusion process for dopant concentration enhancement

Method of filling isolation trenches in a substrate

Method for punching slug from workpiece

Integrated circuits having reduced stress in metallization

Method for reducing stress in the metallization of an integrated circuit

Laser ablation apparatus and method

Selective removal of a single solder ball from an array of solder balls

Laser removal of metal interconnects

GLOBALFOUNDRIES INC

Gate contact structure positioned above an active region with air gaps positioned adjacent the gate structure

Gate cut structure with liner spacer and related method

Methods of forming source/drain contact structures on integrated circuit products

Gate cut method after source/drain metallization

Transistor fins with different thickness gate dielectric

Fin field-effect transistor (FinFET) and method of production thereof

Contacts formed with self-aligned cuts

Gate cut in replacement metal gate process

Self-aligned metal wire on contact structure and method for forming same

Fin-type field effect transistors (FINFETS) with replacement metal gates and methods

Intergrated circuit structure including single diffusion break abutting end isolation region, and methods of forming same

Methods of forming field effect transistors (FETS) with gate cut isolation regions between replacement metal gates

Gate cut integration and related device

Gate cut structures

IC structure with metal cap on cobalt layer and methods of forming same

Late gate cut using selective dielectric deposition

Method of manufacturing finfet devices using narrow and wide gate cut openings in conjunction with a replacement metal gate process

Oxide spacer in a contact over active gate finFET and method of production thereof

INFINEON TECHNOLOGIES AG

Extendible process for improved top oxide layer for DRAM array and the gate interconnects while providing self-aligned gate contacts

Increased polish removal rate of dielectric layers using fixed abrasive pads

NOVELLUS SYSTEMS INC

High throughput chemical vapor deposition process capable of filling high aspect ratio structures

ZHANG JOHN H

Method of repairing probe pads