Inventor

PENNEY DANIEL B

US104 patents

⚠️ This page may combine multiple inventors who share the name “PENNEY DANIEL B”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PENNEY DANIEL B

MICRON TECHNOLOGY INC

Method and circuit for adjusting the timing of ouput data based on an operational mode of output drivers

Apparatuses and methods for adjusting victim data

Apparatuses and methods for access based refresh timing

Apparatuses, systems, and methods for determining extremum numerical values

Apparatuses and methods for tracking victim rows

Apparatuses and methods for monitoring word line accesses

Apparatuses and methods for access based refresh timing

Column repair in memory

Data-strobe input buffers for high-frequency SDRAMS

Method and circuit for adjusting the timing of output data based on an operational mode of output drivers

Method and circuit for adjusting the timing of output data based on an operational mode of output drivers

Method and circuit for adjusting the timing of output data based on an operational mode of output drivers

Memory device having programmable column segmentation to increase flexibility in bit repair

Memory device having programmable column segmentation to increase flexibility in bit repair

Apparatuses and methods for tracking victim rows

Apparatuses, systems, and methods for determining extremum numerical values

Apparatuses and methods for monitoring word line accesses

Apparatuses and methods for adjusting victim data

Memory array accessibility

DFE conditioning for write operations of a memory device

Write leveling a memory device

Write level arbiter circuitry

Apparatuses and methods to selectively perform logical operations

Memory device parallelizer

Internal write adjust for a memory device

Multi-phase clock division

Data strobe gating

Analog multiplexing scheme for decision feedback equalizers

Apparatuses and methods to selectively perform logical operations

Bank to bank data transfer

Write signal launch circuitry for memory drive

Bank to bank data transfer

Apparatuses and methods for storing a data value in a sensing circuitry element

Constant delay zero standby differential logic receiver and method

Predecode column architecture and method

Column redundancy for prefetch

Column redundancy for prefetch

Apparatuses and methods for access based refresh timing

Apparatuses and methods for compensating for crosstalk noise at input receiver circuits

Apparatuses and methods for compensating for crosstalk noise at input receiver circuits

Write leveling

High-speed level shifter

Write leveling for a memory device

DFE conditioning for write operations of a memory device

Gap detection for consecutive write operations of a memory device

Write level initialization synchronization

TEXAS INSTRUMENTS INC

Internal clock multiplication for test time reduction

Clock input buffer with noise suppression

Memory access circuits for test time reduction

LODESTAR LICENSING GROUP LLC

Memory array accessibility