P

Inventor

SCEPANOVIC RANKO

US162 patents
⚠️ This page may combine multiple inventors who share the name “SCEPANOVIC RANKO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LSI LOGIC CORP

47 patents
US6407434B1Jun 18, 2002

Hexagonal architecture

LSI LOGIC CORP245 citations99
US6324674B2Nov 27, 2001

Method and apparatus for parallel simultaneous global and detail routing

LSI LOGIC CORP206 citations99
US6292929B2Sep 18, 2001

Advanced modular cell placement system

LSI LOGIC CORP142 citations99
US6289495B1Sep 11, 2001

Method and apparatus for local optimization of the global routing

LSI LOGIC CORP166 citations99
US6253363B1Jun 26, 2001

Net routing using basis element decomposition

LSI LOGIC CORP153 citations99
US6175950B1Jan 16, 2001

Method and apparatus for hierarchical global routing descend

LSI LOGIC CORP157 citations99
US6155725ADec 5, 2000

Cell placement representation and transposition for integrated circuit physical design automation system

LSI LOGIC CORP174 citations99
US6067409AMay 23, 2000

Advanced modular cell placement system

LSI LOGIC CORP153 citations99
US5973376AOct 26, 1999

Architecture having diamond shaped or parallelogram shaped cells

LSI LOGIC CORP157 citations99
US5822214AOct 13, 1998

CAD for hexagonal architecture

LSI LOGIC CORP297 citations99
US5777360AJul 7, 1998

Hexagonal field programmable gate array architecture

LSI LOGIC CORP338 citations99
US5742086AApr 21, 1998

Hexagonal DRAM array

LSI LOGIC CORP162 citations99
US5650653AJul 22, 1997

Microelectronic integrated circuit including triangular CMOS "nand" gate device

LSI LOGIC CORP175 citations99
US5636125AJun 3, 1997

Computer implemented method for producing optimized cell placement for integrated circiut chip

LSI LOGIC CORP196 citations99
US5495419AFeb 27, 1996

Integrated circuit physical design automation system utilizing optimization process decomposition and parallel processing

LSI LOGIC CORP199 citations99
US6564211B1May 13, 2003

Fast flexible search engine for longest prefix match

LSI LOGIC CORP80 citations98
US6553370B1Apr 22, 2003

Flexible search engine having sorted binary search tree for perfect match

LSI LOGIC CORP114 citations98
US6493658B1Dec 10, 2002

Optimization processing for integrated circuit physical design automation system using optimally switched fitness improvement algorithms

LSI LOGIC CORP104 citations98
US6247167B1Jun 12, 2001

Method and apparatus for parallel Steiner tree routing

LSI LOGIC CORP131 citations98
US6230306B1May 8, 2001

Method and apparatus for minimization of process defects while routing

LSI LOGIC CORP148 citations98
US6154874ANov 28, 2000

Memory-saving method and apparatus for partitioning high fanout nets

LSI LOGIC CORP91 citations98
US6134702AOct 17, 2000

Physical design automation system and process for designing integrated circuit chips using multiway partitioning with constraints

LSI LOGIC CORP90 citations98
US6123736ASep 26, 2000

Method and apparatus for horizontal congestion removal

LSI LOGIC CORP119 citations98
US6058254AMay 2, 2000

Method and apparatus for vertical congestion removal

LSI LOGIC CORP118 citations98
US5898597AApr 27, 1999

Integrated circuit floor plan optimization system

LSI LOGIC CORP133 citations98
US5889329AMar 30, 1999

Tri-directional interconnect architecture for SRAM

LSI LOGIC CORP135 citations98
US5875117AFeb 23, 1999

Simultaneous placement and routing (SPAR) method for integrated circuit physical design automation system

LSI LOGIC CORP91 citations98
US5811863ASep 22, 1998

Transistors having dynamically adjustable characteristics

LSI LOGIC CORP202 citations98
US5557533ASep 17, 1996

Cell placement alteration apparatus for integrated circuit chip physical design automation system

LSI LOGIC CORP118 citations98
US6499003B2Dec 24, 2002

Method and apparatus for application of proximity correction with unitary segmentation

LSI LOGIC CORP88 citations97
US5914887AJun 22, 1999

Congestion based cost factor computing apparatus for integrated circuit physical design automation system

LSI LOGIC CORP176 citations97
US5872380AFeb 16, 1999

Hexagonal sense cell architecture

LSI LOGIC CORP106 citations97
US6260183B1Jul 10, 2001

Method and apparatus for coarse global routing

LSI LOGIC CORP58 citations96
US6197456B1Mar 6, 2001

Mask having an arbitrary complex transmission function

LSI LOGIC CORP90 citations96
US6070108AMay 30, 2000

Method and apparatus for congestion driven placement

LSI LOGIC CORP84 citations96
US5963975AOct 5, 1999

Single chip integrated circuit distributed shared memory (DSM) and communications nodes

LSI LOGIC CORP55 citations96
US5903461AMay 11, 1999

Method of cell placement for an integrated circuit chip comprising chaotic placement and moving windows

LSI LOGIC CORP68 citations96
US5808330ASep 15, 1998

Polydirectional non-orthoginal three layer interconnect architecture

LSI LOGIC CORP54 citations96
US5789770AAug 4, 1998

Hexagonal architecture with triangular shaped cells

LSI LOGIC CORP53 citations96
US5781439AJul 14, 1998

Method for producing integrated circuit chip having optimized cell placement

LSI LOGIC CORP33 citations96
US5745363AApr 28, 1998

Optimization processing for integrated circuit physical design automation system using optimally switched cost function computations

LSI LOGIC CORP70 citations96
US5742510AApr 21, 1998

Simultaneous placement and routing (SPAR) method for integrated circuit physical design automation system

LSI LOGIC CORP61 citations96
US5699265ADec 16, 1997

Physical design automation system and process for designing integrated circuit chips using multiway partitioning with constraints

LSI LOGIC CORP63 citations96
US5682322AOct 28, 1997

Optimization processing for integrated circuit physical design automation system using chaotic fitness improvement method

LSI LOGIC CORP76 citations96
US5661663AAug 26, 1997

Physical design automation system and method using hierarchical clusterization and placement improvement based on complete re-placement of cell clusters

LSI LOGIC CORP66 citations96
US5491641AFeb 13, 1996

Towards optical steiner tree routing in the presence of rectilinear obstacles

LSI LOGIC CORP77 citations95
US6171731B1Jan 9, 2001

Hybrid aerial image simulation

LSI LOGIC CORP103 citations94

(unassigned)

1 patent
US6026223AFeb 15, 2000

Advanced modular cell placement system with overlap remover with minimal noise

269 citations99

LSI LOGIG CORP

1 patent
US6068662AMay 30, 2000

Method and apparatus for congestion removal

LSI LOGIG CORP129 citations96

LIS LOGIC CORP

1 patent
US5578840ANov 26, 1996

Microelectronic integrated circuit structure and method using three directional interconnect routing based on hexagonal geometry

LIS LOGIC CORP188 citations95

Showing the top 50 of 162 patents by PatentIndex Score.