Inventor
ANDREEV ALEXANDER E
US144 patents
⚠️ This page may combine multiple inventors who share the name “ANDREEV ALEXANDER E”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
LSI LOGIC CORP
46 patentsUS6407434B1Jun 18, 2002
Hexagonal architecture
LSI LOGIC CORP245 citations99
US6324674B2Nov 27, 2001
Method and apparatus for parallel simultaneous global and detail routing
LSI LOGIC CORP206 citations99
US6292929B2Sep 18, 2001
Advanced modular cell placement system
LSI LOGIC CORP142 citations99
US6289495B1Sep 11, 2001
Method and apparatus for local optimization of the global routing
LSI LOGIC CORP166 citations99
US6253363B1Jun 26, 2001
Net routing using basis element decomposition
LSI LOGIC CORP153 citations99
US6175950B1Jan 16, 2001
Method and apparatus for hierarchical global routing descend
LSI LOGIC CORP157 citations99
US6067409AMay 23, 2000
Advanced modular cell placement system
LSI LOGIC CORP153 citations99
US5973376AOct 26, 1999
Architecture having diamond shaped or parallelogram shaped cells
LSI LOGIC CORP157 citations99
US5822214AOct 13, 1998
CAD for hexagonal architecture
LSI LOGIC CORP297 citations99
US5777360AJul 7, 1998
Hexagonal field programmable gate array architecture
LSI LOGIC CORP338 citations99
US5742086AApr 21, 1998
Hexagonal DRAM array
LSI LOGIC CORP162 citations99
US5650653AJul 22, 1997
Microelectronic integrated circuit including triangular CMOS "nand" gate device
LSI LOGIC CORP175 citations99
US6564211B1May 13, 2003
Fast flexible search engine for longest prefix match
LSI LOGIC CORP80 citations98
US6553370B1Apr 22, 2003
Flexible search engine having sorted binary search tree for perfect match
LSI LOGIC CORP114 citations98
US6247167B1Jun 12, 2001
Method and apparatus for parallel Steiner tree routing
LSI LOGIC CORP131 citations98
US6230306B1May 8, 2001
Method and apparatus for minimization of process defects while routing
LSI LOGIC CORP148 citations98
US6154874ANov 28, 2000
Memory-saving method and apparatus for partitioning high fanout nets
LSI LOGIC CORP91 citations98
US6134702AOct 17, 2000
Physical design automation system and process for designing integrated circuit chips using multiway partitioning with constraints
LSI LOGIC CORP90 citations98
US6123736ASep 26, 2000
Method and apparatus for horizontal congestion removal
LSI LOGIC CORP119 citations98
US6058254AMay 2, 2000
Method and apparatus for vertical congestion removal
LSI LOGIC CORP118 citations98
US5898597AApr 27, 1999
Integrated circuit floor plan optimization system
LSI LOGIC CORP133 citations98
US5889329AMar 30, 1999
Tri-directional interconnect architecture for SRAM
LSI LOGIC CORP135 citations98
US5811863ASep 22, 1998
Transistors having dynamically adjustable characteristics
LSI LOGIC CORP202 citations98
US5872380AFeb 16, 1999
Hexagonal sense cell architecture
LSI LOGIC CORP106 citations97
US6260183B1Jul 10, 2001
Method and apparatus for coarse global routing
LSI LOGIC CORP58 citations96
US6070108AMay 30, 2000
Method and apparatus for congestion driven placement
LSI LOGIC CORP84 citations96
US5808330ASep 15, 1998
Polydirectional non-orthoginal three layer interconnect architecture
LSI LOGIC CORP54 citations96
US5789770AAug 4, 1998
Hexagonal architecture with triangular shaped cells
LSI LOGIC CORP53 citations96
US5699265ADec 16, 1997
Physical design automation system and process for designing integrated circuit chips using multiway partitioning with constraints
LSI LOGIC CORP63 citations96
US5661663AAug 26, 1997
Physical design automation system and method using hierarchical clusterization and placement improvement based on complete re-placement of cell clusters
LSI LOGIC CORP66 citations96
US5712793AJan 27, 1998
Physical design automation system and process for designing integrated circuit chips using fuzzy cell clusterization
LSI LOGIC CORP64 citations94
US7035844B2Apr 25, 2006
FFS search and edit pipeline separation
LSI LOGIC CORP20 citations93
US6735600B1May 11, 2004
Editing protocol for flexible search engines
LSI LOGIC CORP35 citations93
US6662287B1Dec 9, 2003
Fast free memory address controller
LSI LOGIC CORP24 citations93
US6487698B1Nov 26, 2002
Process, apparatus and program for transforming program language description of an IC to an RTL description
LSI LOGIC CORP21 citations93
US6223332B1Apr 24, 2001
Advanced modular cell placement system with overlap remover with minimal noise
LSI LOGIC CORP28 citations93
US6097073AAug 1, 2000
Triangular semiconductor or gate
LSI LOGIC CORP27 citations93
US6085032AJul 4, 2000
Advanced modular cell placement system with sinusoidal optimization
LSI LOGIC CORP48 citations93
US6038385AMar 14, 2000
Physical design automation system and process for designing integrated circuit chip using "chessboard" and "jiggle" optimization
LSI LOGIC CORP31 citations93
US5835378ANov 10, 1998
Computer implemented method for leveling interconnect wiring density in a cell placement for an integrated circuit chip
LSI LOGIC CORP24 citations93
US5831863ANov 3, 1998
Advanced modular cell placement system with wire length driven affinity system
LSI LOGIC CORP21 citations93
US5808899ASep 15, 1998
Advanced modular cell placement system with cell placement crystallization
LSI LOGIC CORP36 citations93
US5796625AAug 18, 1998
Physical design automation system and process for designing integrated circuit chip using simulated annealing with "chessboard and jiggle" optimization
LSI LOGIC CORP23 citations93
US7039855B2May 2, 2006
Decision function generator for a Viterbi decoder
LSI LOGIC CORP20 citations92
US6941533B2Sep 6, 2005
Clock tree synthesis with skew for memory devices
LSI LOGIC CORP28 citations92
US6941494B1Sep 6, 2005
Built-in test for multiple memory circuits
LSI LOGIC CORP24 citations92
(unassigned)
1 patentLSI LOGIG CORP
1 patentLIS LOGIC CORP
1 patentLSI CORP
1 patentShowing the top 50 of 144 patents by PatentIndex Score.