Inventor

TRAN THANG MINH

US30 patents

⚠️ This page may combine multiple inventors who share the name “TRAN THANG MINH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TRAN THANG MINH

SIMPLEX MICRO INC

Multi-threading microprocessor with a time counter for statically dispatching instructions

Microprocessor with time counter for statically dispatching instructions

Register scoreboard for a microprocessor with a time counter for statically dispatching instructions

Microprocessor with time counter for statically dispatching instructions with phantom registers

Time-resource matrix for a microprocessor with time counter for statically dispatching instructions

Microprocessor with apparatus and method for handling of instructions with long throughput

Method and apparatus for a scalable microprocessor with time counter

Vector processor with extended vector registers

Microprocessor with speculative and in-order register sets

Microprocessor with apparatus and method for replaying load instructions

Executing phantom loops in a microprocessor

Microprocessor with odd and even register sets

Vector processor with vector data buffer

Microprocessor with time count based instruction execution and replay

Microprocessor with a time counter for statically dispatching extended instructions

Out-of-order execution of loop instructions in a microprocessor

Vector coprocessor with time counter for statically dispatching instructions

Microprocessor with shared read and write buses and instruction issuance to multiple register sets in accordance with a time counter

Microprocessor with non-cacheable memory load prediction

ANDES TECH CORPORATION

Microprocessor with shared functional unit for executing multi-type instructions

Microprocessor having self-resetting register scoreboard

Microprocessor with pipeline control for executing of instruction at a preset future time

Processor having read shifter and controlling method using the same

Processor having latency shifter and controlling method using the same

Apparatus and method for using instruction translation look-aside buffers in the branch target buffer

Microprocessor and method for speculatively issuing load/store instruction with non-deterministic access time using scoreboard

(unassigned)

Method and apparatus for executing plurality of operations per clock cycle in a single processing unit with a self-timed and self-enabled distributed clock

Multiple-bit random-access memory array

TEXAS INSTRUMENTS INC

Loop detection and capture in the instruction queue

XI JINWEN

Application specific instruction set processor for digital radio processor receiving chain signal processing