P

Inventor

RINGE MATTHIAS

DE46 patents
⚠️ This page may combine multiple inventors who share the name “RINGE MATTHIAS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IBM

45 patents
US10326435B2Jun 18, 2019

Dynamic control of edge shift for duty cycle correction

IBM24 citations93
US7865855B2Jan 4, 2011

Method and system for generating a layout for an integrated electronic circuit

IBM10 citations84
US7526743B2Apr 28, 2009

Method for routing data paths in a semiconductor chip with a plurality of layers

IBM9 citations84
US10564664B2Feb 18, 2020

Integrated skew control

IBM6 citations83
US10148259B1Dec 4, 2018

Skew sensor with enhanced reliability

IBM6 citations83
US10063222B1Aug 28, 2018

Dynamic control of edge shift for duty cycle correction

IBM14 citations83
US8037441B2Oct 11, 2011

Gridded-router based wiring on a non-gridded library

IBM17 citations82
US10546094B2Jan 28, 2020

Generating a layout for an integrated circuit

IBM1 citations73
US10355683B2Jul 16, 2019

Correcting duty cycle and compensating for active clock edge shift

IBM2 citations73
US10348279B2Jul 9, 2019

Skew control

IBM3 citations73
US9916409B2Mar 13, 2018

Generating a layout for an integrated circuit

IBM2 citations73
US11256284B2Feb 22, 2022

Integrated skew control

IBM2 citations72
US11163002B2Nov 2, 2021

Burn-in resilient integrated circuit for processors

IBM2 citations72
US11022998B2Jun 1, 2021

Optimally driving non-uniform clock mesh loads

IBM2 citations72
US10348278B2Jul 9, 2019

Method and apparatus for clock skew control with low jitter in an integrated circuit

IBM2 citations72
US10158351B1Dec 18, 2018

Skew control apparatus and algorithm using a low pass filter

IBM2 citations72
US8566771B1Oct 22, 2013

Automation of interconnect and routing customization

IBM5 citations72
US10175297B2Jan 8, 2019

Measuring a slew rate on-chip

IBM4 citations71
US9306547B2Apr 5, 2016

Duty cycle adjustment with error resiliency

IBM3 citations71
US7844931B2Nov 30, 2010

Method and computer system for optimizing the signal time behavior of an electronic circuit design

IBM6 citations69
US11921157B2Mar 5, 2024

Burn-in resilient integrated circuit for processors

IBM0 citations62
US11088684B2Aug 10, 2021

Calibrating internal pulses in an integrated circuit

IBM0 citations62
US11025239B2Jun 1, 2021

Static compensation of an active clock edge shift for a duty cycle correction circuit

IBM0 citations62
US10892744B2Jan 12, 2021

Correcting duty cycle and compensating for active clock edge shift

IBM0 citations62
US10684642B2Jun 16, 2020

Adaptive clock mesh wiring

IBM1 citations62
US10110205B2Oct 23, 2018

Method and apparatus for clock skew control with low jitter in an integrated circuit

IBM1 citations62
US8912824B1Dec 16, 2014

Method and apparatus for detecting rising and falling transitions of internal signals of an integrated circuit

IBM3 citations62
US7886245B2Feb 8, 2011

Structure for optimizing the signal time behavior of an electronic circuit design

IBM4 citations58
US10756714B2Aug 25, 2020

Skew control

IBM0 citations52
US9953124B2Apr 24, 2018

Generating a layout for an integrated circuit

IBM0 citations52
US11176304B2Nov 16, 2021

Routing a cell of a semiconductor chip

IBM0 citations51
US11113446B2Sep 7, 2021

Yield improving leaf cells optimization for semiconductor netlists

IBM0 citations51
US10804889B2Oct 13, 2020

Double compression avoidance

IBM0 citations51
US10651834B2May 12, 2020

Method and apparatus for clock skew control with low jitter in an integrated circuit

IBM0 citations51
US10622981B2Apr 14, 2020

Static compensation of an active clock edge shift for a duty cycle correction circuit

IBM0 citations51
US10594307B2Mar 17, 2020

Skew sensor with enhanced reliability

IBM0 citations51
US10581417B2Mar 3, 2020

Skew sensor with enhanced reliability

IBM0 citations51
US10469063B2Nov 5, 2019

Method and apparatus for clock skew control with low jitter in an integrated circuit

IBM0 citations51
US10361689B2Jul 23, 2019

Static compensation of an active clock edge shift for a duty cycle correction circuit

IBM0 citations51
US10312892B2Jun 4, 2019

On-chip waveform measurement

IBM0 citations51
US10298217B2May 21, 2019

Double compression avoidance

IBM0 citations51
US10263606B2Apr 16, 2019

On-chip waveform measurement

IBM0 citations51
US8937494B1Jan 20, 2015

Method and apparatus for detecting rising and falling transitions of internal signals of an integrated circuit

IBM1 citations51
US9754063B2Sep 5, 2017

Reducing dynamic clock skew and/or slew in an electronic circuit

IBM0 citations41
US8949761B2Feb 3, 2015

Techniques for routing signal wires in an integrated circuit design

IBM0 citations41

FRICKE NIELS

1 patent