Inventor

CHANG KUO-TUNG

US132 patents

⚠️ This page may combine multiple inventors who share the name “CHANG KUO-TUNG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHANG KUO-TUNG

MOTOROLA INC

Self-aligned, split-gate EEPROM device

Cross-point eeprom memory array

Split-gate memory device and method for accessing the same

Process of making EEPROM memory device having a sidewall spacer floating gate electrode

EEPROM memory device having a sidewall spacer floating gate electrode and process

Non-volatile memory, method of manufacture, and method of programming

Split-gate vertically oriented EEPROM device and process

Fabrication process for a 1-transistor EEPROM memory device capable of low-voltage operation

Method of making and accessing split gate memory device

EEPROM cell with isolation transistor and methods for making and operating the same

Method for making an EEPROM cell with isolation transistor

Electrically programmable read-only memory array

Process for forming electrically programmable read-only memory cell with a merged select/control gate

Non-volatile memory with a serial transistor structure with isolated well and method of operation

Method of building an EPROM cell without drain disturb and reduced select gate resistance

Method for operating a memory array

Nonvolatile memory having overerase protection

Non-linear charge pump

Semiconductor device and method of operating it

Nonvolatile memory circuit and structure

Method of making a nonvolatile memory device with five transistors

CYPRESS SEMICONDUCTOR CORP

Split-gate flash cell formed on recessed substrate

Memory first process flow and device

Suppression of program disturb with bit line and select gate voltage regulation

Method of forming high-voltage transistor with thin gate poly

Embedded non-volatile memory device and fabrication method of the same

Contacts for semiconductor devices

Method of forming high-voltage transistor with thin gate poly

Non-volatile memory array with memory gate line and source line scrambling

SPANSION LLC

Memory first process flow and device

Dual charge storage node memory device and methods for fabricating such device

Semiconductor device having a pad metal layer and a lower metal layer that are electrically coupled, whereas apertures are formed in the lower metal layer below a center area of the pad metal layer

Reduction of leakage current and program disturbs in flash memory devices

Memory device and methods for its fabrication

Methods for fabricating a split charge storage node semiconductor memory

System and method for improving mesa width in a semiconductor device

Method and apparatus for coupling to a source line in a memory device

ADVANCED MICRO DEVICES INC

Use of high-K dielectric material in modified ONO structure for semiconductor devices

Use of high-k dielectric materials in modified ONO structure for semiconductor devices

Memory device and method of making

BPSG, SA-CVD liner/P-HDP gap fill

Narrow wide spacer

Non-volatile memory dielectric as charge pump dielectric

HYUNDAI ELECTRONICS IND

Self-aligned dual-bit split gate (DSG) flash EEPROM cell

Method of making a self-aligned dual-bit split gate (DSG) flash EEPROM cell

BRIGHT MICROELECTRONICS INC

Flash eprom memory circuit having source side programming

MA YUEH Y

Self-aligned dual-bit split gate (DSG) flash EEPROM cell

SPANSION L L C

Flash memory device having increased over-erase correction efficiency and robustness against device variations

ADVANCED MIRCO DEVICES INC

Method and apparatus for eliminating word line bending by source side implantation

FASL LLC

Electrostatic discharge performance of a silicon structure and efficient use of area with electrostatic discharge protective device under the pad approach and adjustment of via configuration thereto to control drain junction resistance