Inventor
LIU YAOCHENG
US28 patents
⚠️ This page may combine multiple inventors who share the name “LIU YAOCHENG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
20 patentsUS7696000B2Apr 13, 2010
Low defect Si:C layer with retrograde carbon profile
IBM124 citations98
US7524740B1Apr 28, 2009
Localized strain relaxation for strained Si directly on insulator
IBM70 citations98
US7888197B2Feb 15, 2011
Method of forming stressed SOI FET having doped glass box layer using sacrificial stressed layer
IBM29 citations92
US7279758B1Oct 9, 2007
N-channel MOSFETs comprising dual stressors, and methods for forming the same
IBM24 citations91
US7714358B2May 11, 2010
Semiconductor structure and method of forming the structure
IBM12 citations84
US7709910B2May 4, 2010
Semiconductor structure for low parasitic gate capacitance
IBM8 citations81
US7932144B2Apr 26, 2011
Semiconductor structure and method of forming the structure
IBM4 citations63
US7741658B2Jun 22, 2010
Self-aligned super stressed PFET
IBM3 citations63
US7675118B2Mar 9, 2010
Semiconductor structure with enhanced performance using a simplified dual stress liner configuration
IBM2 citations63
US7632724B2Dec 15, 2009
Stressed SOI FET having tensile and compressive device regions
IBM4 citations63
US7598147B2Oct 6, 2009
Method of forming CMOS with Si:C source/drain by laser melting and recrystallization
IBM5 citations63
US7473608B2Jan 6, 2009
N-channel MOSFETs comprising dual stressors, and methods for forming the same
IBM4 citations61
US7615435B2Nov 10, 2009
Semiconductor device and method of manufacture
IBM4 citations60
US7838932B2Nov 23, 2010
Raised STI structure and superdamascene technique for NMOSFET performance enhancement with embedded silicon carbon
IBM1 citations52
US7667263B2Feb 23, 2010
Semiconductor structure including doped silicon carbon liner layer and method for fabrication thereof
IBM0 citations52
US7655551B2Feb 2, 2010
Control of poly-Si depletion in CMOS via gas phase doping
IBM1 citations52
US7504309B2Mar 17, 2009
Pre-silicide spacer removal
IBM0 citations52
US7485519B2Feb 3, 2009
After gate fabrication of field effect transistor having tensile and compressive regions
IBM1 citations52
US7473594B2Jan 6, 2009
Raised STI structure and superdamascene technique for NMOSFET performance enhancement with embedded silicon carbon
IBM1 citations52
US7473626B2Jan 6, 2009
Control of poly-Si depletion in CMOS via gas phase doping
IBM0 citations52
LIU YAOCHENG
3 patentsUS8217423B2Jul 10, 2012
Structure and method for mobility enhanced MOSFETs with unalloyed silicide
LIU YAOCHENG97 citations97
US8642434B2Feb 4, 2014
Structure and method for mobility enhanced MOSFETS with unalloyed silicide
LIU YAOCHENG14 citations92
US9059316B2Jun 16, 2015
Structure and method for mobility enhanced MOSFETs with unalloyed silicide
LIU YAOCHENG0 citations51