Inventor

NATARAJ BINDIGANAVALE S

US75 patents

⚠️ This page may combine multiple inventors who share the name “NATARAJ BINDIGANAVALE S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NATARAJ BINDIGANAVALE S

NETLOGIC MICROSYSTEMS INC

Method for longest prefix matching in a content addressable memory

Multiport content addressable memory device and timing signals

Ternary content addressable memory cell

Method and apparatus for cascading content addressable memory devices

Content addressable memory with error signaling

Content addressable memory with latching sense amplifier

Content addressable memory with selectable mask write mode

Memory storage cell based array of counters

Method and apparatus for determining a longest prefix match in a segmented content addressable memory device

Method and apparatus for implementing a learn instruction in a depth cascaded content addressable memory system

Dynamically partitioned CAM array

Low power content addressable memory

Method and apparatus for determining an exact match in a ternary content addressable memory device

Row redundancy in a content addressable memory

Ternary content addressable memory with compare operand selected according to mask value

Method and apparatus for performing a read next highest priority match instruction in a content addressable memory device

Row redundancy for content addressable memory

Row redundancy in a content addressable memory

Method and apparatus for implementing a learn instruction in a content addressable memory device

Content addressable memory with block-programmable mask write mode, word width and priority

Content addressable memory with programmable word width and programmable priority

Memory device having bit line leakage compensation

Content addressable memory with multi-row write function

Classless interdomain routing using binary content addressable memory having mask bits and mask valid bits

Method and apparatus for performing packet classification for policy-based packet routing

Synchronous content addressable memory

Content addressable memory with mode-selectable match detect timing

Classless interdomain routing using binary content addressable memory

Bit line control circuit for a content addressable memory

Content addressable memory having dynamic match resolution

Word line driver circuit for a content addressable memory

Synchronous content addressable memory

Timing execution of compare instructions in a synchronous content addressable memory

Method and apparatus for determining an exact match in a content addressable memory device

Method and apparatus for performing a read next highest priority match instruction in a content addressable memory device

Method of generating an almost full flag and a full flag in a content addressable memory

Spare address decoder

Match line control circuit for content addressable memory

Adaptive match line charging

Precharge circuits and methods for content addressable memory (CAM) and related devices

Configurable non-volatile logic structure for characterizing an integrated circuit device

Content addressable memory with programmable word width and programmable priority

Ternary content addressable memory device

Segmented content addressable memory device having pipelined compare operations

Low power content addressable memory device having selectable cascaded array segments

NETLOGIC MICROSYSTEMS

Method and apparatus for simultaneously performing a plurality of compare operations in content addressable memory device

Match line control circuit for content addressable memory

NET LOGIC MICROSYSTEMS

Method and apparatus for selective match line pre-charging in a content addressable memory

KHANNA SANDEEP

Incremental adaptive match line charging with calibration

INFORMATION STORAGE DEVICES

Message management methods and apparatus