Inventor

CHERABUDDI RAJASEKHAR

US25 patents

⚠️ This page may combine multiple inventors who share the name “CHERABUDDI RAJASEKHAR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHERABUDDI RAJASEKHAR

SUN MICROSYSTEMS INC

Dynamically allocated cache memory for a multi-processor unit

Inclusion vector architecture for a level two cache

Cache memory array which stores two-way set associative data

Low-latency, high-throughput, integrated cache coherent I/O system for a single-chip processor

Apparatus including a fetch unit to include branch history information to increase performance of multi-cylce pipelined branch prediction structures

System and method for using a page tracking buffer to reduce main memory latency in a computer system

Simplified writeback handling

Method for reducing number of register file ports in a wide instruction issue processor

Method and apparatus for resolving multiple branches

Bi-level branch target prediction scheme with fetch address prediction

Method and apparatus for branch target prediction

Apparatus and method to improve primary memory latencies using an eviction buffer to store write requests

Central processing unit and method for improving instruction cache miss latencies using an instruction buffer which conditionally stores additional addresses

DMA transfer method for a system including a single-chip processor with a processing core and a device interface in different clock domains

Method to reduce memory latencies by performing two levels of speculation

Apparatus and method to speculatively initiate primary memory accesses

Method for storing data in two-way set associative odd and even banks of a cache memory

Bi-level branch target prediction scheme with mux select prediction

Superscalar processor for retiring multiple instructions in working register file by changing the status bits associated with each execution result to identify valid data

Apparatus and method to efficiently abort and restart a primary memory access

Yield improvement through probe-based cache size reduction

Method and apparatus for performing multiple branch predictions per cycle

BRANSCOME JEREMY L

Methods and systems for hardware acceleration of streamed database operations and queries based on multiple hardware accelerators

Methods and systems for hardware acceleration of database operations and queries based on multiple hardware accelerators

BROCADE COMM SYSTEMS INC

Isolation of data, control, and management traffic in a storage area network