Inventor

HADDAD SAMEER

US59 patents

⚠️ This page may combine multiple inventors who share the name “HADDAD SAMEER”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HADDAD SAMEER

ADVANCED MICRO DEVICES INC

Dual source side polysilicon select gate structure and programming method utilizing single tunnel oxide for nand array flash memory

Flash memory array architecture having staggered metal lines

Non-volatile semiconductor memory device including assymetrically nitrogen doped gate oxide

Methods for forming nitrogen-rich regions in a floating gate and interpoly dielectric layer in a non-volatile semiconductor memory device

Methods and arrangements for introducing nitrogen into a tunnel oxide in a non-volatile semiconductor memory device

Memory cell programming with controlled current injection

Non-volatile memory structure including protection and structure for maintaining threshold stability

Pocket implant for complementary bit disturb improvement and charging improvement of SONOS memory cell

Ramp source hot-hole programming for trap based non-volatile memory devices

Innovative narrow gate formation for floating gate flash technology

Method of channel hot electron programming for short channel NOR flash arrays

Dual source side polysilicon select gate structure utilizing single tunnel oxide for NAND array flash memory

Methods for forming nitrogen-rich regions in non-volatile semiconductor memory devices

Flash memory array architecture and method of programming, erasing and reading thereof

Source side boron implanting and diffusing device architecture for deep sub 0.18 micron flash memory

Performance in flash memory devices

Low column leakage flash memory array

Method of programming memory cells

Method and system for using a spacer to offset implant damage and reduce lateral diffusion in flash memory devices

Nonvolatile memory structure for programmable logic devices

Dual source side polysilicon select gate structure and programming method utilizing single tunnel oxide for NAND array flash memory

Bitline implant utilizing dual poly

Memory array with buried bit lines

Source side boron implant and drain side MDD implant for deep sub 0.18 micron flash memory

Method for decreasing the discharge time of a flash EPROM cell

Reduction of sector connecting line capacitance using staggered metal lines

Method and system for using a spacer to offset implant damage and reduce lateral diffusion in flash memory devices

Reduced silicon gouging and common source line resistance in semiconductor devices

SPANSION LLC

Method of programming a resistive memory device

Resistive memory device with improved data retention

Memory first process flow and device

LDC implant for mirrorbit to improve Vt roll-off and form sharper junction

Resistive memory array using P-I-N diode select device and methods of fabrication thereof

Method of selecting operating characteristics of a resistive memory device

Test structures for development of metal-insulator-metal (MIM) devices

Erase verification circuitry for simultaneously and consecutively verifying a plurality of odd and even-numbered flash memory transistors and method thereof

Memory device with improved data retention

Memory device with improved data retention

Method of fabricating metal-insulator-metal (MIM) device with stable data retention

Metal-insulator-metal (MIM) device and method of formation thereof

Method of erasing a resistive memory device

Pin diode device and architecture

Erase, programming and leakage characteristics of a resistive memory device

Metal-insualtor-metal (MIM) device and method of formation thereof

CYPRESS SEMICONDUCTOR CORP

Memory first process flow and device

Memory first process flow and device

Memory first process flow and device

Memory first process flow and device

(unassigned)

Using floating gate devices as select gate devices for NAND flash memory and its bias scheme

KAZA SWAROOP

Method of programming, erasing and repairing a memory device