Inventor

THURGATE TIMOTHY

US46 patents

⚠️ This page may combine multiple inventors who share the name “THURGATE TIMOTHY”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

THURGATE TIMOTHY

ADVANCED MICRO DEVICES INC

Memory device with an alternating Vss interconnection

Very low thermal budget channel implant process for semiconductors

Operational approach for the suppression of bi-directional tunnel oxide stress of a flash cell

Two bit flash cell with two floating gate regions

Nitride plug to reduce gate edge lifting

Diode fabrication for ESD/EOS protection

Source side boron implanting and diffusing device architecture for deep sub 0.18 micron flash memory

Deposited screen oxide for reducing gate edge lifting

Method for forming a dielectric spacer in a non-volatile memory device

Solid-source doping for source/drain to eliminate implant damage

Biasing scheme to reduce stress on non-selected cells during read

High voltage transistor with high gated diode breakdown, low body effect and low leakage

Method for inhibiting tunnel oxide growth at the edges of a floating gate during semiconductor device processing

Method for inhibiting tunnel oxide growth at the edges of a floating gate during semiconductor device processing

Method for reducing short channel effects in memory cells and related structure

Structure and method to reduce drain induced barrier lowering

Source side boron implant and drain side MDD implant for deep sub 0.18 micron flash memory

High voltage transistor with high gated diode breakdown, low body effect and low leakage

Lateral doped channel

Memory cell array with staggered local inter-connect structure

SPANSION LLC

Reduction of leakage current and program disturbs in flash memory devices

Semiconductor memory comprising dual charge storage nodes and methods for its fabrication

Methods for fabricating flash memory devices

Structure and method for low Vss resistance and reduced DIBL in a floating gate memory cell

Multi-phase wordline erasing for flash memory

Selective application of word line bias to minimize fringe effects in electromagnetic fields during erase of nonvolatile memory

Selective application of word line bias to minimize fringe effects in electromagnetic fields during erase of nonvolatile memory

Method of increasing erase speed in memory arrays

Memory array with memory cells having reduced short channel effects

Dual storage node memory devices and methods for fabricating the same

Using thick spacer for bitline implant then remove

Deep bitline implant to avoid program disturb

BANNA SRINIVASA RAO

Semiconductor memory device and method for biasing same

Techniques for providing a semiconductor memory device

Techniques for providing a semiconductor memory device

MICRON TECHNOLOGY INC

Techniques for providing a semiconductor memory device

Techniques for providing a semiconductor memory device

Techniques for providing a semiconductor memory device

CYPRESS SEMICONDUCTOR CORP

Tilted implant for poly resistors

Charge-trapping memory device

ADVANCED MICTRO DEVICES INC

High voltage transistor with high gated diode breakdown voltage

PARIKH SUKETU ARUN

Method of forming an electronic device including forming a charge storage element in a trench of a workpiece

LEE CHUNGHO

Semiconductor memory comprising dual charge storage nodes and methods for its fabrication

THURGATE TIMOTHY

Apparatus and method for extended nitride layer in a flash memory

SINHA SHANKAR

Memory device with buried bit line structure

SUGINO RINJI

Memory device protection layer