Inventor

RANDOLPH MARK W

US41 patents

⚠️ This page may combine multiple inventors who share the name “RANDOLPH MARK W”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

RANDOLPH MARK W

ADVANCED MICRO DEVICES INC

Use of high-K dielectric material in modified ONO structure for semiconductor devices

Uniform bitline strapping of a non-volatile memory cell

Program algorithm including soft erase for SONOS memory device

Overerase correction method

Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same

Method of improving dynamic reference tracking for flash memory unit

System for programming a non-volatile memory cell

Replacing layers of an intergate dielectric layer with high-K material for improved scalability

Memory device and method using positive gate stress to recover overerased cell

Pocket implant for complementary bit disturb improvement and charging improvement of SONOS memory cell

Method of protecting a memory array from charge damage during fabrication

Dual cell memory device having a top dielectric stack

Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same

Method of controlling program threshold voltage distribution of a dual cell memory device

Non-volatile memory cell and method of programming for improved data retention

Flash memory device having four-bit cells

Staggered bitline strapping of a non-volatile memory cell

Staggered bitline strapping of a non-volatile memory cell

Select transistor architecture for a virtual ground non-volatile memory cell array

Memory device having a thin top dielectric and method of erasing same

Method of fabricating a planar structure charge trapping memory cell array with rectangular gates and reduced bit line resistance

Pre-charge method for reading a non-volatile memory cell

Method and system for erasing a nitride memory device

Memory device with reduced operating voltage having dielectric stack

Method of determining charge loss activation energy of a memory array

Method for improving electrostatic discharge (ESD) robustness

Method for reading a non-volatile memory cell adjacent to an inactive region of a non-volatile memory cell array

Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same

Recess channel flash architecture for reduced short channel effect

Method for fabricating nitride memory cells using a floating gate fabrication process

Source side boron implant and drain side MDD implant for deep sub 0.18 micron flash memory

Memory cell array with staggered local inter-connect structure

SPANSION LLC

Silicided buried bitline process for a non-volatile memory cell

Applying negative gate voltage to wordlines adjacent to wordline associated with read or verify to reduce adjacent wordline disturb

Room temperature drift suppression via soft program after erase

Multi-pass soft programming

MELIK-MARTIROSIAN ASHOT

Memory device having trapezoidal bitlines and method of fabricating same

Memory device having trapezoidal bitlines and method of fabricating same

ADVANCE MICRO DEVICES INC

Method for reading a non-volatile memory cell

HAMILTON DARLENE G

Extending flash memory data retension via rewrite refresh

DAVIS BRADLEY MARC

Leakage reducing writeline charge protection circuit