Inventor
FARRELL ROBERT L
US27 patents
⚠️ This page may combine multiple inventors who share the name “FARRELL ROBERT L”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
21 patentsUS6785829B1Aug 31, 2004
Multiple operating frequencies in a processor
INTEL CORP92 citations98
US5228134AJul 13, 1993
Cache memory integrated circuit for use with a synchronous central processor bus and an asynchronous memory bus
INTEL CORP121 citations96
US5355467AOct 11, 1994
Second level cache controller unit and system
INTEL CORP211 citations95
US5293603AMar 8, 1994
Cache subsystem for microprocessor based computer system with synchronous and asynchronous data path
INTEL CORP84 citations95
US4570220AFeb 11, 1986
High speed parallel bus and data transfer method
INTEL CORP194 citations94
US6988211B2Jan 17, 2006
System and method for selecting a frequency and voltage combination from a table using a selection field and a read-only limit field
INTEL CORP45 citations92
US6091426AJul 18, 2000
Integrating data scaling and buffering functions to minimize memory requirement
INTEL CORP30 citations92
US5953411ASep 14, 1999
Method and apparatus for maintaining audio sample correlation
INTEL CORP23 citations92
US4807109AFeb 21, 1989
High speed synchronous/asynchronous local bus and data transfer method
INTEL CORP58 citations90
US5488639AJan 30, 1996
Parallel multistage synchronization method and apparatus
INTEL CORP16 citations71
US9824412B2Nov 21, 2017
Position-only shading pipeline
INTEL CORP5 citations70
US7937525B2May 3, 2011
Method and apparatus for decoding a virtual machine control structure identification
INTEL CORP4 citations62
US7269711B2Sep 11, 2007
Methods and apparatus for address generation in processors
INTEL CORP3 citations60
US10204051B2Feb 12, 2019
Technique to share information among different cache coherency domains
INTEL CORP0 citations52
US10078590B2Sep 18, 2018
Technique to share information among different cache coherency domains
INTEL CORP0 citations52
US10002455B2Jun 19, 2018
Optimized depth buffer cache apparatus and method
INTEL CORP0 citations52
US9946650B2Apr 17, 2018
Technique to share information among different cache coherency domains
INTEL CORP0 citations52
US9412195B2Aug 9, 2016
Constant buffer size multi-sampled anti-aliasing depth compression
INTEL CORP1 citations52
US9035962B2May 19, 2015
Technique to share information among different cache coherency domains
INTEL CORP0 citations52
US9569882B2Feb 14, 2017
Four corner high performance depth test
INTEL CORP1 citations51
US7249243B2Jul 24, 2007
Control word prediction and varying recovery upon comparing actual to set of stored words
INTEL CORP0 citations42
OFFEN ZEEV
3 patentsUS8643660B2Feb 4, 2014
Technique to share information among different cache coherency domains
OFFEN ZEEV2 citations61
US9035960B2May 19, 2015
Technique to share information among different cache coherency domains
OFFEN ZEEV0 citations51
US9035959B2May 19, 2015
Technique to share information among different cache coherency domains
OFFEN ZEEV0 citations51