Inventor

STELLARI FRANCO

US69 patents

⚠️ This page may combine multiple inventors who share the name “STELLARI FRANCO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

STELLARI FRANCO

IBM

Minimum-spacing circuit design and layout for PICA

System and method for virtual control of laboratory equipment

Enhanced signal observability for circuit analysis

Method for the characterization and monitoring of integrated circuits

Measuring and predicting VLSI chip reliability and failure

System and method for estimation of integrated circuit signal characteristics using optical measurements

Process variation on-chip sensor

Machine learning-based circuit board inspection

RRAM filament location based on NIR emission

Automated scan chain diagnostics using emission

Automated scan chain diagnostics using emission

Integrated time dependent dielectric breakdown reliability testing

Method and apparatus for diagnosing broken scan chain based on leakage light emission

Method and apparatus for diagnosing broken scan chain based on leakage light emission

Integrated circuit identification

Integrated circuit identification

Method for the characterization and monitoring of integrated circuits

Method for the characterization and monitoring of integrated circuits

Detection of hardware trojan using light emissions with sacrificial mask

Non-destructive analysis to determine use history of processor

ReRAM analog PUF using filament location

Physical unclonable function device with phase change

Automated scan chain diagnostics using emission

Method and system for quickly identifying circuit components in an emission image

Enhanced signal observability for circuit analysis

Optical trigger for PICA technique

Method and apparatus for light-controlled circuit characterization

RRAM filament spatial localization using a laser stimulation

Method for the characterization and monitoring of integrated circuits

Integrated circuit identification

Method for the characterization and monitoring of integrated circuits

Integrated circuit identification

Apparatus and methods for packaging electronic devices for optical testing

Apparatus and methods for packaging electronic devices for optical testing

System and method for estimation of integrated circuit signal characteristics using optical measurements

Dielectric breakdown monitor

Scan chain latch design that improves testability of integrated circuits

Using photonic emission to develop electromagnetic emission models

Scan chain latch design that improves testability of integrated circuits

STELLARI FRANCO

Method and apparatus for creating time-resolved emission images of integrated circuits using a single-point single-photon detector and a scanning system

Registering measured images to layout data

Navigating analytical tools using layout software

Creating emission images of integrated circuits

Navigating analytical tools using layout software

SONG PEILIN

Method and system for quickly identifying circuit components in an emission image

Self-adjusting critical path timing of multi-core VLSI chip

POLONSKY STANISLAV

Constructing variability maps by correlating off-state leakage emission images to layout information

BERNSTEIN KERRY

Detecting chip alterations with light emission

AINSPAN HERSCHEL A

Minimum-spacing circuit design and layout for PICA

CHEN JIFENG

Integrated time dependent dielectric breakdown reliability testing