Inventor

CHEN BI-LING

TW14 patents

⚠️ This page may combine multiple inventors who share the name “CHEN BI-LING”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

VANGUARD INT SEMICONDUCT CORP

13 patents

US5956594ASep 21, 1999

Method for simultaneously forming capacitor plate and metal contact structures for a high density DRAM device

VANGUARD INT SEMICONDUCT CORP106 citations98

US6159839ADec 12, 2000

Method for fabricating borderless and self-aligned polysilicon and metal contact landing plugs for multilevel interconnections

VANGUARD INT SEMICONDUCT CORP146 citations97

US6476488B1Nov 5, 2002

Method for fabricating borderless and self-aligned polysilicon and metal contact landing plugs for multilevel interconnections

VANGUARD INT SEMICONDUCT CORP49 citations94

US6025255AFeb 15, 2000

Two-step etching process for forming self-aligned contacts

VANGUARD INT SEMICONDUCT CORP91 citations93

US6239011B1May 29, 2001

Method of self-aligned contact hole etching by fluorine-containing discharges

VANGUARD INT SEMICONDUCT CORP22 citations92

US6184081B1Feb 6, 2001

Method of fabricating a capacitor under bit line DRAM structure using contact hole liners

VANGUARD INT SEMICONDUCT CORP57 citations92

US6140240AOct 31, 2000

Method for eliminating CMP induced microscratches

VANGUARD INT SEMICONDUCT CORP19 citations92

US6080662AJun 27, 2000

Method for forming multi-level contacts using a H-containing fluorocarbon chemistry

VANGUARD INT SEMICONDUCT CORP20 citations92

US6037211AMar 14, 2000

Method of fabricating contact holes in high density integrated circuits using polysilicon landing plug and self-aligned etching processes

VANGUARD INT SEMICONDUCT CORP37 citations92

US6565759B1May 20, 2003

TAIWAN SEMICONDUCTOR MFG

1 patent

US6670279B1Dec 30, 2003

Method of forming shallow trench isolation with rounded corners and divot-free by using in-situ formed spacers

TAIWAN SEMICONDUCTOR MFG14 citations84

CHEN BI-LING

VANGUARD INT SEMICONDUCT CORP

Method for simultaneously forming capacitor plate and metal contact structures for a high density DRAM device

Method for fabricating borderless and self-aligned polysilicon and metal contact landing plugs for multilevel interconnections

Method for fabricating borderless and self-aligned polysilicon and metal contact landing plugs for multilevel interconnections

Two-step etching process for forming self-aligned contacts

Method of self-aligned contact hole etching by fluorine-containing discharges

Method of fabricating a capacitor under bit line DRAM structure using contact hole liners

Method for eliminating CMP induced microscratches

Method for forming multi-level contacts using a H-containing fluorocarbon chemistry

Method of fabricating contact holes in high density integrated circuits using polysilicon landing plug and self-aligned etching processes

Etching process

Method of forming a contact hole in a semiconductor device

Method for producing multi-level contacts

Method for forming multi-level contacts

TAIWAN SEMICONDUCTOR MFG

Method of forming shallow trench isolation with rounded corners and divot-free by using in-situ formed spacers