Inventor

NAYAK ANUP

US44 patents

⚠️ This page may combine multiple inventors who share the name “NAYAK ANUP”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NAYAK ANUP

CYPRESS SEMICONDUCTOR CORP

Programmable interconnect matrix architecture for complex programmable logic device

PLD configuration port architecture and logic

USB type-C sideband signal interface circuit

Configurable and power-optimized integrated gate-driver for USB power-delivery and type-C SoCs

System and method for staging concurrent accesses to a memory address location via a single port using a high speed sampling clock

Programmable interconnect matrix architecture for complex programmable logic device

Architecture and logic to control a device without a JTAG port through a device with a JTAG port

Configurable power controller

Self-biased gate driver architecture

USB type-c signal interface circuit

USB type-C signal interface circuit

USB power control analog subsystem architecture

USB type-C signal interface circuit

Power supply architecture for USB-C controllers

Programmable gate driver control in USB power delivery

Power supply architecture for USB-C controllers

Configurable and power-optimized integrated gate-driver for USB power-delivery and type-C SoCs

Power supply architecture for USB-C controllers

Configurable and power-optimized integrated gate-driver for USB power-delivery and type-C SoCs

Circuit for generating silicon ID for PLDS

JTAG instruction register and decoder for PLDS

Method and apparatus to save power in USB repeaters/re-timers

Asynchronous arbiter with bounded resolution time and predictable output state

PLD configuration architecture

Programmable VBUS discharge in USB power delivery

Method and apparatus to save power in USB repeaters/re-timers

Configuration bit read/write data shift register

USB type-C sideband signal interface circuit

Method and device for selecting one of multiple clock signals based on frequency differences of such clock signals

Method and system for identifying configuration circuit addresses in a schematic hierarchy

USB power control analog subsystem architecture

Startup regulator using voltage buffer to stabilize power supply voltage

Degenerate network for PLD and plane

Multilevel circuit implementation for a tristate bus

Macro-cell flip-flop with scan-in input

Method and system for generating a bit order data structure of configuration bits from a schematic hierarchy

ACCENTURE GLOBAL SOLUTIONS LTD

Generating attack graphs in agile security platforms

Generating attack graphs in agile security platforms

Criticality analysis of attack graphs

Generating attack graphs in agile security platforms

Process risk calculation based on hardness of attack paths

KHODABANDEHLOU HAMID

Architectures for supporting communication and access between multiple host devices and one or more common functions

SANCHETI SANJAY KUMAR

Circuit and method for dynamic in-rush current control in a power management circuit

NAYAK ANUP

Low power USB 2.0 subsystem