Inventor
CHADWICK LAURA S
US8 patents
⚠️ This page may combine multiple inventors who share the name “CHADWICK LAURA S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
7 patentsUS7073100B2Jul 4, 2006
Method for testing embedded DRAM arrays
IBM16 citations90
US7890906B2Feb 15, 2011
Method of laying out integrated circuit design based on known polysilicon perimeter densities of individual cells
IBM8 citations83
US7810054B2Oct 5, 2010
Method of optimizing power usage of an integrated circuit design by tuning selective voltage binning cut point
IBM11 citations82
US7877714B2Jan 25, 2011
System and method to optimize semiconductor power by integration of physical design timing and product performance measurements
IBM10 citations81
US7849433B2Dec 7, 2010
Integrated circuit with uniform polysilicon perimeter density, method and design structure
IBM7 citations73
US7237165B2Jun 26, 2007
Method for testing embedded DRAM arrays
IBM9 citations71
US7805693B2Sep 28, 2010
IC chip design modeling using perimeter density to electrical characteristic correlation
IBM2 citations62