Inventor
DREIBELBIS JEFFREY H
US21 patents
⚠️ This page may combine multiple inventors who share the name “DREIBELBIS JEFFREY H”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
20 patentsUS6233184B1May 15, 2001
Structures for wafer level test and burn-in
IBM102 citations98
US6507237B2Jan 14, 2003
Low-power DC voltage generator system
IBM44 citations96
US6337595B1Jan 8, 2002
Low-power DC voltage generator system
IBM52 citations96
US7984329B2Jul 19, 2011
System and method for providing DRAM device-level repair via address remappings external to the device
IBM41 citations92
US6577548B1Jun 10, 2003
Self timing interlock circuit for embedded DRAM
IBM25 citations92
US6426904B2Jul 30, 2002
Structures for wafer level test and burn-in
IBM43 citations92
US4730122AMar 8, 1988
Power supply adapter systems
IBM34 citations92
US4709162ANov 24, 1987
Off-chip driver circuits
IBM27 citations92
US5019772AMay 28, 1991
Test selection techniques
IBM26 citations91
US7073100B2Jul 4, 2006
Method for testing embedded DRAM arrays
IBM16 citations90
US6452848B1Sep 17, 2002
Programmable built-in self test (BIST) data generator for semiconductor memory devices
IBM29 citations90
US7737766B2Jun 15, 2010
Two stage voltage boost circuit, IC and design structure
IBM8 citations84
US6766468B2Jul 20, 2004
Memory BIST and repair
IBM14 citations84
US6044024AMar 28, 2000
Interactive method for self-adjusted access on embedded DRAM memory macros
IBM10 citations73
US5463335AOct 31, 1995
Power up detection circuits
IBM11 citations72
US7237165B2Jun 26, 2007
Method for testing embedded DRAM arrays
IBM9 citations71
US7401281B2Jul 15, 2008
Remote BIST high speed test and redundancy calculation
IBM2 citations60
US7733161B2Jun 8, 2010
Voltage boost system, IC and design structure
IBM0 citations52
US7710195B2May 4, 2010
Two stage voltage boost circuit with precharge circuit preventing leakage, IC and design structure
IBM1 citations52
US7472325B2Dec 30, 2008
Method for segmenting BIST functionality in an embedded memory array into remote lower-speed executable instructions and local higher-speed executable instructions
IBM1 citations50