Inventor · disambiguated record
Paul M. Harvey
Also filed as: HARVEY PAUL · HARVEY PAUL M · HARVEY PAUL MARLAN
23 granted patents·6 pending applications·496 citations·filing 1996–2012
95Inventor score
Top patents by PatentIndex Score
29 records- 0194US6140707ALaminated integrated circuit package3M INNOVATIVE PROPERTIES CO·Filed 1998·Granted Oct 31, 2000·221 cites·6 claims
- 0293US6876088B2Flex-based IC package construction employing a balanced laminationIBM·Filed 2003·Granted Apr 5, 2005·77 cites·6 claims
- 0389US7064412B2Electronic package with integrated capacitor3M INNOVATIVE PROPERTIES CO·Filed 2000·Granted Jun 20, 2006·60 cites·16 claims
- 0484US7482654B2MOSgated power semiconductor device with source field electrodeINT RECTIFIER CORP·Filed 2005·Granted Jan 27, 2009·13 cites·19 claims
- 0580US8791372B2Reducing impedance discontinuity in packagesHARVEY PAUL M·Filed 2012·Granted Jul 29, 2014·4 cites·16 claims
- 0680US7203608B1Impedane measurement of chip, package, and board power supply system using pseudo impulse responseIBM·Filed 2006·Granted Apr 10, 2007·10 cites·20 claims
- 0778US8440917B2Method and apparatus to reduce impedance discontinuity in packagesHARVEY PAUL M·Filed 2007·Granted May 14, 2013·7 cites·13 claims
- 0873US7390717B2Trench power MOSFET fabrication using inside/outside spacersINT RECTIFIER CORP·Filed 2005·Granted Jun 24, 2008·6 cites·20 claims
- 0972US7687391B2Electrically optimized and structurally protected via structure for high speed signalsIBM·Filed 2006·Granted Mar 30, 2010·5 cites·12 claims
- 1069US7816754B2Ball grid array package construction with raised solder ball padsIBM·Filed 2007·Granted Oct 19, 2010·3 cites·13 claims
- 1169US6153508AMulti-layer circuit having a via matrix interlayer connection and method for fabricating the same3M INNOVATIVE PROPERTIES CO·Filed 1998·Granted Nov 28, 2000·32 cites·8 claims
- 1269US5753976AMulti-layer circuit having a via matrix interlayer connectionMINNESOTA MINING & MFG·Filed 1996·Granted May 19, 1998·33 cites·14 claims
- 1365US7492570B2Systems and methods for reducing simultaneous switching noise in an integrated circuitTOSHIBA KK·Filed 2005·Granted Feb 17, 2009·3 cites·16 claims
- 1455US7253510B2Ball grid array package construction with raised solder ball padsIBM·Filed 2003·Granted Aug 7, 2007·5 cites·15 claims
- 1554US7368353B2Trench power MOSFET with reduced gate resistanceINT RECTIFIER CORP·Filed 2004·Granted May 6, 2008·7 cites·7 claims
- 1652US8222739B2System to improve coreless package connectionsHARVEY PAUL M·Filed 2009·Granted Jul 17, 2012·0 cites·17 claims
- 1751US7911049B2Electrically optimized and structurally protected via structure for high speed signalsIBM·Filed 2008·Granted Mar 22, 2011·0 cites·12 claims
- 1848US8338949B2System to improve coreless package connectionsHARVEY PAUL M·Filed 2012·Granted Dec 25, 2012·0 cites·13 claims
- 1946US7388275B2Electronic package with integrated capacitor3M INNOVATIVE PROPERTIES CO·Filed 2006·Granted Jun 17, 2008·0 cites·4 claims
- 2046US6867121B2Method of apparatus for interconnecting a relatively fine pitch circuit layer and adjacent power plane(s) in a laminated constructionIBM·Filed 2003·Granted Mar 15, 2005·2 cites·16 claims
- 2143US8153516B2Method of ball grid array package construction with raised solder ball padsHARVEY PAUL MARLAN·Filed 2010·Granted Apr 10, 2012·0 cites·10 claims
- 2241US2010017158A1Generating worst case bit patterns for simultaneous switching noise (ssn) in digital systemsIBM·Filed 2008·Application pending·0 cites
- 2340US2009008133A1Patterned Circuits and Method for Making SameBULLARD JEFFREY W·Filed 2004·Application pending·0 cites
- 2439US8631706B2Noise suppressor for semiconductor packagesGRUENDLER NICKOLAUS J·Filed 2010·Granted Jan 21, 2014·0 cites·21 claims
- 2539US2009302874A1Method and apparatus for signal probe contact with circuit board viasIBM·Filed 2008·Application pending·0 cites
- 2638US6150071AFabrication process for flex circuit applications3M INNOVATIVE PROPERTIES CO·Filed 1998·Granted Nov 21, 2000·8 cites·16 claims
- 2737US2004201970A1Chip interconnection method and apparatusIBM·Filed 2003·Application pending·0 cites
- 2836US2012175763A1Integrated circuit packaging including auxiliary circuitryHARVEY PAUL M·Filed 2011·Application pending·0 cites
- 2934US2001052647A1Laminated integrated circuit package3M INNOVATIVE PROPERTIES CO·Filed 2001·Application pending·0 cites
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