Inventor · disambiguated record
Paul D. Agnello
Also filed as: AGNELLO PAUL D · AGNELLO PAUL DAVID
38 granted patents·3 pending applications·1,375 citations·filing 1991–2010
98Inventor score
Top patents by PatentIndex Score
41 records- 0198US7358166B2Relaxed, low-defect SGOI for strained Si CMOS applicationsIBM·Filed 2005·Granted Apr 15, 2008·62 cites·23 claims
- 0298US6472258B1Double gate trench transistorIBM·Filed 2000·Granted Oct 29, 2002·162 cites·9 claims
- 0396US6406962B1Vertical trench-formed dual-gate FET device structure and method for creationIBM·Filed 2001·Granted Jun 18, 2002·139 cites·40 claims
- 0495US5796166ATasin oxygen diffusion barrier in multilayer structuresIBM·Filed 1996·Granted Aug 18, 1998·122 cites·7 claims
- 0592US5576579ATasin oxygen diffusion barrier in multilayer structuresIBM·Filed 1995·Granted Nov 19, 1996·83 cites·4 claims
- 0691US6287913B1Double polysilicon process for providing single chip high performance logic and compact embedded memory structureIBM·Filed 1999·Granted Sep 11, 2001·76 cites·34 claims
- 0790US5776823ATasin oxygen diffusion barrier in multilayer structuresIBM·Filed 1996·Granted Jul 7, 1998·67 cites·6 claims
- 0890US5624869AMethod of forming a film for a multilayer Semiconductor device for improving thermal stability of cobalt silicide using platinum or nitrogenIBM·Filed 1994·Granted Apr 29, 1997·70 cites·40 claims
- 0988US6440851B1Method and structure for controlling the interface roughness of cobalt disilicideIBM·Filed 1999·Granted Aug 27, 2002·57 cites·24 claims
- 1088US6255217B1Plasma treatment to enhance inorganic dielectric adhesion to copperIBM·Filed 1999·Granted Jul 3, 2001·78 cites·18 claims
- 1187US6686617B2Semiconductor chip having both compact memory and high performance logicIBM·Filed 2001·Granted Feb 3, 2004·36 cites·8 claims
- 1285US5608266AThin film for a multilayer semiconductor device for improving thermal stability and a method thereofIBM·Filed 1995·Granted Mar 4, 1997·58 cites·13 claims
- 1381US6946373B2Relaxed, low-defect SGOI for strained Si CMOS applicationsIBM·Filed 2002·Granted Sep 20, 2005·24 cites·22 claims
- 1481US5654570ACMOS gate stackIBM·Filed 1995·Granted Aug 5, 1997·43 cites·4 claims
- 1580US7265417B2Method of fabricating semiconductor side wall finIBM·Filed 2004·Granted Sep 4, 2007·20 cites·12 claims
- 1680US6828630B2CMOS device on ultrathin SOI with a deposited raised source/drain, and a method of manufactureIBM·Filed 2003·Granted Dec 7, 2004·23 cites·19 claims
- 1777US7361556B2Method of fabricating semiconductor side wall finIBM·Filed 2006·Granted Apr 22, 2008·5 cites·10 claims
- 1876US6891228B2CMOS device on ultrathin SOI with a deposited raised source/drain, and a method of manufactureIBM·Filed 2004·Granted May 10, 2005·18 cites·6 claims
- 1976US5897349AMethod for fabricating a capped gate conductorIBM·Filed 1996·Granted Apr 27, 1999·34 cites·18 claims
- 2075US6261951B1Plasma treatment to enhance inorganic dielectric adhesion to copperIBM·Filed 1999·Granted Jul 17, 2001·34 cites·19 claims
- 2172US6593660B2Plasma treatment to enhance inorganic dielectric adhesion to copperIBM·Filed 2001·Granted Jul 15, 2003·11 cites·12 claims
- 2270US6916729B2Salicide formation methodIBM·Filed 2003·Granted Jul 12, 2005·16 cites·11 claims
- 2369US8227792B2Relaxed low-defect SGOI for strained SI CMOS applicationsAGNELLO PAUL D·Filed 2008·Granted Jul 24, 2012·4 cites·13 claims
- 2468US5378651AComprehensive process for low temperature epitaxial growthIBM·Filed 1993·Granted Jan 3, 1995·39 cites·12 claims
- 2566US6563131B1Method and structure of a dual/wrap-around gate field effect transistorIBM·Filed 2000·Granted May 13, 2003·12 cites·18 claims
- 2664US7683434B2Preventing cavitation in high aspect ratio dielectric regions of semiconductor deviceIBM·Filed 2008·Granted Mar 23, 2010·2 cites·7 claims
- 2764US6274446B1Method for fabricating abrupt source/drain extensions with controllable gate electrode overlapIBM·Filed 1999·Granted Aug 14, 2001·19 cites·18 claims
- 2861US7163864B1Method of fabricating semiconductor side wall finIBM·Filed 2000·Granted Jan 16, 2007·7 cites·8 claims
- 2959US6407436B1Semiconductor device with abrupt source/drain extensions with controllable gate electrode overlapIBM·Filed 2001·Granted Jun 18, 2002·7 cites·6 claims
- 3056US7081676B2Structure for controlling the interface roughness of cobalt disilicideIBM·Filed 2003·Granted Jul 25, 2006·5 cites·8 claims
- 3156US5227330AComprehensive process for low temperature SI epit axial growthIBM·Filed 1991·Granted Jul 13, 1993·24 cites·14 claims
- 3250US7696573B2Multiple crystallographic orientation semiconductor structuresIBM·Filed 2007·Granted Apr 13, 2010·0 cites·13 claims
- 3347US6809030B2Method and structure for controlling the interface roughness of cobalt disilicideIBM·Filed 2002·Granted Oct 26, 2004·2 cites·9 claims
- 3444US7993990B2Multiple crystallographic orientation semiconductor structuresIBM·Filed 2010·Granted Aug 9, 2011·0 cites·12 claims
- 3543US5635242AMethod and apparatus for preventing rupture and contamination of an ultra-clean APCVD reactor during shutdownIBM·Filed 1995·Granted Jun 3, 1997·8 cites·6 claims
- 3643US5487783AMethod and apparatus for preventing rupture and contamination of an ultra-clean APCVD reactor during shutdownIBM·Filed 1994·Granted Jan 30, 1996·8 cites·10 claims
- 3742US7459384B2Preventing cavitation in high aspect ratio dielectric regions of semiconductor deviceIBM·Filed 2004·Granted Dec 2, 2008·0 cites·15 claims
- 3839US7112845B2Double gate trench transistorIBM·Filed 2002·Granted Sep 26, 2006·0 cites·13 claims
- 3935US2002142526A1Structures and methods to minimize plasma charging damage in silicon on insulator devicesIBM·Filed 2001·Application pending·0 cites
- 4033US2005048732A1Method to produce transistor having reduced gate heightIBM·Filed 2003·Application pending·0 cites
- 4130US2003042551A1Partially removable spacer with salicide formationFiled 1999·Application pending·0 cites
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