Inventor
YOUNG JAY T
US17 patents
⚠️ This page may combine multiple inventors who share the name “YOUNG JAY T”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
XILINX INC
15 patentsUS7509617B1Mar 24, 2009
Design methodology to support relocatable bit streams for dynamic partial reconfiguration of FPGAs to reduce bit stream memory requirements
XILINX INC70 citations97
US7890917B1Feb 15, 2011
Method and apparatus for providing secure intellectual property cores for a programmable logic device
XILINX INC47 citations93
US6760899B1Jul 6, 2004
Dedicated resource placement enhancement
XILINX INC24 citations91
US7941777B1May 10, 2011
Generating a module interface for partial reconfiguration design flows
XILINX INC13 citations83
US7600210B1Oct 6, 2009
Method and apparatus for modular circuit design for a programmable logic device
XILINX INC12 citations83
US7480842B1Jan 20, 2009
Method and apparatus for reducing the number of test designs for device testing
XILINX INC9 citations83
US7149997B1Dec 12, 2006
Routing with frame awareness to minimize device programming time and test cost
XILINX INC17 citations83
US7058919B1Jun 6, 2006
Methods of generating test designs for testing specific routing resources in programmable logic devices
XILINX INC15 citations83
US6944809B2Sep 13, 2005
Methods of resource optimization in programmable logic devices to reduce test time
XILINX INC13 citations82
US7249335B1Jul 24, 2007
Methods of routing programmable logic devices to minimize programming time
XILINX INC9 citations73
US7673272B1Mar 2, 2010
Method and apparatus for generating an area constraint for a module in a programmable logic device
XILINX INC5 citations62
US7299430B1Nov 20, 2007
Reducing design execution run time bit stream size for device testing
XILINX INC6 citations62
US7143384B1Nov 28, 2006
Methods of routing programmable logic devices to minimize programming time
XILINX INC4 citations62
US10467373B2Nov 5, 2019
Method of selecting routing resources in a multi-chip integrated circuit device
XILINX INC0 citations51
US10715149B1Jul 14, 2020
Configurable logic block (CLB) internal routing architecture for enhanced local routing and clocking improvements
XILINX INC0 citations38