Inventor
SUBAG JACOB
IL26 patents
⚠️ This page may combine multiple inventors who share the name “SUBAG JACOB”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
25 patentsUS10372416B2Aug 6, 2019
Multiply-accumulate “0” data gating
INTEL CORP15 citations93
US11037330B2Jun 15, 2021
Low rank matrix compression
INTEL CORP10 citations85
US10467795B2Nov 5, 2019
Sub-graph in frequency domain and dynamic selection of convolution implementation on a GPU
INTEL CORP6 citations83
US11704564B2Jul 18, 2023
Real time context dependent deep learning
INTEL CORP1 citations72
US11620766B2Apr 4, 2023
Low rank matrix compression
INTEL CORP1 citations72
US11600035B2Mar 7, 2023
Sub-graph in frequency domain and dynamic selection of convolution implementation on a GPU
INTEL CORP1 citations72
US11087206B2Aug 10, 2021
Smart memory handling and data management for machine learning networks
INTEL CORP3 citations72
US10922556B2Feb 16, 2021
Storage system of DNN outputs for black box
INTEL CORP4 citations72
US10853035B2Dec 1, 2020
Multiply-accumulate “0” data gating
INTEL CORP2 citations72
US10606559B2Mar 31, 2020
Multiply-accumulate “0” data gating
INTEL CORP1 citations72
US11238338B2Feb 1, 2022
Real time context dependent deep learning
INTEL CORP3 citations71
US11599777B2Mar 7, 2023
Scheduling configuration for deep learning networks
INTEL CORP3 citations70
US12223427B2Feb 11, 2025
Real time context dependent deep learning
INTEL CORP0 citations62
US12131507B2Oct 29, 2024
Low rank matrix compression
INTEL CORP0 citations62
US11886984B2Jan 30, 2024
Variable precision and mix type representation of multiple layers in a network
INTEL CORP0 citations62
US11763140B2Sep 19, 2023
Smart memory handling and data management for machine learning networks
INTEL CORP0 citations62
US11669719B2Jun 6, 2023
Storage system of DNN outputs for black box
INTEL CORP0 citations62
US11656846B2May 23, 2023
Multiply-accumulate “0” data gating
INTEL CORP0 citations62
US11250610B2Feb 15, 2022
Sub-graph in frequency domain and dynamic selection of convolution implementation on a GPU
INTEL CORP0 citations62
US11093822B2Aug 17, 2021
Variable precision and mix type representation of multiple layers in a network
INTEL CORP1 citations62
US12033063B2Jul 9, 2024
Scheduling configuration for deep learning networks
INTEL CORP0 citations59
US10762685B2Sep 1, 2020
Sub-graph in frequency domain and dynamic selection of convolution implementation on a GPU
INTEL CORP0 citations51
US9536342B2Jan 3, 2017
Automatic partitioning techniques for multi-phase pixel shading
INTEL CORP0 citations51
US10559112B2Feb 11, 2020
Hybrid mechanism for efficient rendering of graphics images in computing environments
INTEL CORP0 citations49
US9218679B2Dec 22, 2015
Reduced bitcount polygon rasterization
INTEL CORP0 citations48