Inventor
BEHAR MICHAEL
IL25 patents
Patents
25 patentsUS10372416B2Aug 6, 2019
Multiply-accumulate “0” data gating
INTEL CORP15 citations93
US11080611B2Aug 3, 2021
Compression for deep learning in case of sparse values mapped to non-zero value
INTEL CORP6 citations83
US10467795B2Nov 5, 2019
Sub-graph in frequency domain and dynamic selection of convolution implementation on a GPU
INTEL CORP6 citations83
US10726583B2Jul 28, 2020
System and method of encoding and decoding feature maps and weights for a convolutional neural network
INTEL CORP10 citations82
US12147914B2Nov 19, 2024
Compression for deep learning in case of sparse values mapped to non-zero value
INTEL CORP1 citations72
US11763183B2Sep 19, 2023
Compression for deep learning in case of sparse values mapped to non-zero value
INTEL CORP2 citations72
US11704564B2Jul 18, 2023
Real time context dependent deep learning
INTEL CORP1 citations72
US11600035B2Mar 7, 2023
Sub-graph in frequency domain and dynamic selection of convolution implementation on a GPU
INTEL CORP1 citations72
US10853035B2Dec 1, 2020
Multiply-accumulate “0” data gating
INTEL CORP2 citations72
US10606559B2Mar 31, 2020
Multiply-accumulate “0” data gating
INTEL CORP1 citations72
US11675630B2Jun 13, 2023
Methods and apparatus to configure heterogenous components in an accelerator
INTEL CORP2 citations71
US11238338B2Feb 1, 2022
Real time context dependent deep learning
INTEL CORP3 citations71
US10210137B2Feb 19, 2019
Binary multiplier for binary vector factorization
INTEL CORP3 citations69
US12223427B2Feb 11, 2025
Real time context dependent deep learning
INTEL CORP0 citations62
US11656846B2May 23, 2023
Multiply-accumulate “0” data gating
INTEL CORP0 citations62
US11250610B2Feb 15, 2022
Sub-graph in frequency domain and dynamic selection of convolution implementation on a GPU
INTEL CORP0 citations62
US12217101B2Feb 4, 2025
Methods and apparatus to configure heterogenous components in an accelerator
INTEL CORP0 citations60
US11847497B2Dec 19, 2023
Methods and apparatus to enable out-of-order pipelined execution of static mapping of a workload
INTEL CORP0 citations60
US11231963B2Jan 25, 2022
Methods and apparatus to enable out-of-order pipelined execution of static mapping of a workload
INTEL CORP1 citations60
US11151074B2Oct 19, 2021
Methods and apparatus to implement multiple inference compute engines
INTEL CORP0 citations56
US10762685B2Sep 1, 2020
Sub-graph in frequency domain and dynamic selection of convolution implementation on a GPU
INTEL CORP0 citations51
US9875213B2Jan 23, 2018
Methods, apparatus, instructions and logic to provide vector packed histogram functionality
INTEL CORP0 citations51
US9189398B2Nov 17, 2015
Apparatus and method for memory-mapped register caching
INTEL CORP0 citations51
US12131250B2Oct 29, 2024
Inner product convolutional neural network accelerator
INTEL CORP0 citations47
US11422939B2Aug 23, 2022
Shared read—using a request tracker as a temporary read cache
INTEL CORP0 citations45