Inventor

LIU DAVID K Y

US52 patents

⚠️ This page may combine multiple inventors who share the name “LIU DAVID K Y”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LIU DAVID K Y

ADVANCED MICRO DEVICES INC

Channel hot-carrier page write

Method for protecting a stacked gate edge in a semiconductor device from self aligned source (SAS) etch

Method protecting a stacked gate edge in a semiconductor device from self aligned source (SAS) etch

Semiconductor circuit including non-ESD transistors with reduced degradation due to an impurity implant

Method and system for protecting a stacked gate edge in a semiconductor device from self-aligned source (sas) etch in a semiconductor device

Method for making semiconductor circuit including non-ESD transistors with reduced degradation due to an impurity implant

Method for providing device isolation and off-state leakage current for a semiconductor device

High energy buried layer implant to provide a low resistance p-well in a flash EPROM array

Method and system for protecting a stacked gate edge in a semi-conductor device from self aligned source (SAS) etch in a semi-conductor device

Method and test structure for determining gouging in a flash EPROM cell during SAS etch

Method for decreasing the discharge time of a flash EPROM cell

PROGRESSANT TECHNOLOGIES INC

Charge trapping device and method for implementing a transistor having a negative differential resistance mode

CMOS compatible process for making a tunable negative differential resistance (NDR) device

CMOS-process compatible, tunable NDR (negative differential resistance) device and method of operating same

Charge trapping device

Method for configuring a device to include a negative differential resistance (NDR) characteristic

Negative differential resistance (NDR) device and method of operating same

Method for making both a negative differential resistance (NDR) device and a non-NDR device using a common MOS process

CMOS process compatible, tunable negative differential resistance (NDR) device and method of operating same

LIU DAVID K Y

Incrementally programmable non-volatile memory

Common drain non-volatile multiple-time programmable memory

Non-volatile one-time—programmable and multiple-time programmable memory configuration circuit

Method of operating incrementally programmable non-volatile memory

Capacitively coupled logic gate

Two terminal programmable hot channel electron non-volatile memory

Zero cost NVM cell using high voltage devices in analog process

Non-volatile one-time-programmable and multiple-time programmable memory configuration circuit

JONKER LLC

Method of operating incrementally programmable non-volatile memory

Method of operating ephemeral peripheral device

One time accessible (OTA) non-volatile memory

Ephemeral peripheral device

Ephemeral storage elements, circuits, and systems

Ephemeral peripheral device

Method of operating incrementally programmable non-volatile memory

AMIC TECHNOLOGY INC

Circuit and method for erasing flash memory array

Circuit and method for erasing flash memory array

Circuit for detecting both charge gain and charge loss properties in a non-volatile memory array

Flash memory cell &amp; array with improved pre-program and erase characteristics

Flash EPROM using junction hot hole injection for erase

(unassigned)

Highly scalable FLASH EEPROM cell

Flash memory cell and a new method for sensing the content of the new memory cell

Flash memory cell and a new method for sensing the content of the new memory cell

ALTERA CORP

High voltage MOS devices with high gated-diode breakdown voltage and punch-through voltage

High voltage MOS devices with high gated-diode breakdown voltage and punch-through voltage

TEXAS INSTRUMENTS INC

Sublithographic antifuse

Sublithographic antifuse method for manufacturing

INVENSAS CORP

Non-volatile one-time-programmable and multiple-time programmable memory configuration circuit

Method of operating integrated circuit embedded with non-volatile programmable memory having variable coupling related application data

PROGRESSENT TECHNOLOGIES INC

Charge trapping device and method for implementing a transistor having a configurable threshold

SYNOPSYS INC

Variable threshold semiconductor device and method of operating same

Flash memory cell & array with improved pre-program and erase characteristics