Inventor

CHAN KEVIN K

US208 patents

⚠️ This page may combine multiple inventors who share the name “CHAN KEVIN K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHAN KEVIN K

IBM

Self-aligned nanotube field effect transistor and method of fabricating same

Method of forming a fully-depleted SOI ( silicon-on-insulator) MOSFET having a thinned channel region

Self-aligned double-gate MOSFET by selective epitaxy and silicon wafer bonding techniques

Strained silicon CMOS on hybrid crystal orientations

Fully-depleted SOI MOSFETs with low source and drain resistance and minimal overlap capacitance using a recessed channel damascene gate process

Interfacial oxidation process for high-k gate dielectric process integration

finFETS and methods of making same

Method for producing a doped nitride film, doped oxide film and other doped films

Doped nitride film, doped oxide film and other doped films

Chemical treatment to retard diffusion in a semiconductor overlayer

Damascene double-gate FET

Self-aligned silicide process for silicon sidewall source and drain contacts

Method utilizing CMP to fabricate double gate MOSFETS with conductive sidewall contacts

CMOS device structure with improved PFET gate electrode

Lateral bipolar junction transistor with abrupt junction and compound buried oxide

Semiconductor structures including an integrated finFET with deep trench capacitor and methods of manufacture

Semiconductor-on-insulator (SOI) lateral heterojunction bipolar transistor having a wide band gap emitter/collector which are epitaxially grown

Thin box metal backgate extremely thin SOI device

Structure and method of fabricating FinFET

High performance strained silicon FinFETs device and method for forming same

Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI)

MOSFET structure with multiple self-aligned silicide contacts

Split poly-SiGe/poly-Si alloy gate stack

Strained silicon-channel MOSFET using a damascene gate process

Method for forming junction on insulator (JOI) structure

Method for increasing the capacitance of a trench capacitor

Semiconductor-on-insulator (SOI) lateral heterojunction bipolar transistor having a wide band gap emitter/collector which are epitaxially grown

Self-aligned nanotube field effect transistor

FinFET with longitudinal stress in a channel

Vertical nanotube field effect transistor

Self-aligned nanotube field effect transistor and method of fabricating same

Bipolar transistor structure with self-aligned raised extrinsic base and methods

Bipolar transistor structure with self-aligned raised extrinsic base and methods

Self-aligned isolation double-gate FET

Damascene double-gate FET

Self-aligned double-gate MOSFET by selective epitaxy and silicon wafer bonding techniques

Method and structure for ultra-low contact resistance CMOS formed by vertically self-aligned COSI2 on raised source drain Si/SiGe device

Self-aligned silicide process for reduction of Si consumption in shallow junction and thin SOI electronic devices

Two-step MOSFET gate formation for high-density devices

Plasma enhanced chemical vapor processing system using hollow cathode effect

CAI JIN

Horizontal polysilicon-germanium heterojunction bipolar transistor

Germanium lateral bipolar junction transistor

Germanium lateral bipolar junction transistor

SOI lateral bipolar junction transistor having a wide band gap emitter contact

NING TAK H

SOI SiGe-base lateral bipolar junction transistor

SOI SiGe-base lateral bipolar junction transistor

APPENZELLER JOERG

Method of fabricating self-aligned nanotube field effect transistor

Self-aligned nanotube field effect transistor

INFINEON TECHNOLOGIES AG

Method to fill deep trench structures with void-free polysilicon or silicon

CHAN KEVIN K

Field effect transistor device