Inventor

RIM KERN

US160 patents

⚠️ This page may combine multiple inventors who share the name “RIM KERN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

RIM KERN

IBM

High-performance CMOS devices on hybrid crystal oriented substrates

Strained silicon on insulator structures

Method to fabricate a strained Si CMOS structure using selective epitaxial deposition of Si after device isolation formation

Localized strain relaxation for strained Si directly on insulator

Strained-silicon CMOS device and method

Multiple gate MOSFET structure with strained Si Fin body

Semiconductor-on-insulator lateral p-i-n photodetector with a reflecting mirror and backside contact and method for forming the same

MOSFET structure with high mechanical stress in the channel

Methods for forming lateral trench optical detectors

Method and structure for forming a localized SOI finFET

Strained finFET with an electrically isolated channel

Pre-epitaxial disposable spacer integration scheme with very low temperature selective epitaxy for enhanced device performance

Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI)

MOSFET structure with multiple self-aligned silicide contacts

Double silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) structures

High performance stress-enhance MOSFET and method of manufacture

Stress engineering using dual pad nitride with selective SOI device architecture

Method for forming a SiGe or SiGeC gate selectively in a complementary MIS/MOS FET device

Structure and method for advanced bulk fin isolation

Structure and method for compressively strained silicon germanium fins for pFET devices and tensily strained silicon fins for nFET devices

Structure and method for advanced bulk fin isolation

Finfet with oxidation-induced stress

Strained finFET with an electrically isolated channel

Complex circuits utilizing fin structures

FinFET with oxidation-induced stress

Fin structure with varying isolation thickness

Method and structure for forming a localized SOI finFET

Method and apparatus for post silicide spacer removal

Ultra thin channel (UTC) MOSFET structure formed on BOX regions having different depths and different thicknesses beneath the UTC and source/drain regions and method of manufacture thereof

Strained-silicon CMOS device and method

MOSFET structure with multiple self-aligned silicide contacts

Semiconductor structure and method of forming the structure

High performance stress-enhance MOSFET and method of manufacture

Silicon/silcion germaninum/silicon body device with embedded carbon dopant

Formation of improved SOI substrates using bulk semiconductor wafers

Method of forming substantially L-shaped silicide contact for a semiconductor device

QUALCOMM INC

Integrating a gate-all-around (GAA) field-effect transistor(s) (FET(S)) and a finFET(s) on a common substrate of a semiconductor die

Semiconductor device having a gap defined therein

Silicon germanium FinFET formation by Ge condensation

Integrated circuits including a FinFET and a nanostructure FET

Device and method to connect gate regions separated using a gate cut

Self-aligned structure

GLOBALFOUNDRIES INC

Methods of forming fin isolation regions on finFET semiconductor devices using an oxidation-blocking layer of material

FinFET and nanowire semiconductor devices with suspended channel regions and gate structures surrounding the suspended channel regions

Methods of forming fin isolation regions on FinFET semiconductor devices using an oxidation-blocking layer of material and by performing a fin-trimming process

Methods of forming isolated germanium-containing fins for a FinFET semiconductor device

LIU YAOCHENG

Structure and method for mobility enhanced MOSFETs with unalloyed silicide

Structure and method for mobility enhanced MOSFETS with unalloyed silicide

SAMSUNG ELECTRONICS CO LTD

Embedded stressor structure and process

CHANG PAUL

Compact model for device/circuit/chip leakage current (IDDQ) calculation including process induced uplift factors