Inventor

CHUANG HARRY

US94 patents

⚠️ This page may combine multiple inventors who share the name “CHUANG HARRY”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHUANG HARRY

TAIWAN SEMICONDUCTOR MFG

Method for gap filling in a gate last process

Methodology to characterize metal sheet resistance of copper damascene process

Standard cell architecture and methods with variable design rules

Localized slots for stress relieve in copper

Integrating a first contact structure in a gate last process

Modifying work function in PMOS devices by counter-doping

Localized slots for stress relieve in copper

Photoresist etch back method for gate last process

Method for gate height control in a gate last process

Contact scheme for MOSFETs

Dummy patterns in integrated circuit fabrication

Dishing-free gap-filling with multiple CMPs

Metal fuse structure for saving layout area

Semiconductor device with high-K/dual metal gate

Integrating a capacitor in a metal gate last process

High-k metal gate CMOS patterning method

Spacer shape engineering for void-free gap-filling process

Poly resistor and poly eFuse design for replacement gate technology

Reducing device performance drift caused by large spacings between active regions

Method for gate height control in a gate last process

Method for tuning a work function of high-k metal gate devices

Method and apparatus for semiconductor device with improved source/drain junctions

MOS devices with source/drain regions having stressed regions and non-stressed regions

Controlling gate formation by removing dummy gate structures

Method and apparatus for semiconductor device with improved source/drain junctions

Method of forming a novel top-metal fuse structure

Method for making a semiconductor device having metal gate stacks

Method for a gate last process

Chemical mechanical polishing (CMP) method for gate last process

Method for improving design window

CHUANG HARRY

Integrated circuit metal gate structure and method of fabrication

Strained transistor with optimized drive current and method of forming

Integrating the formation of I/O and core MOS devices with MOS capacitors and resistors

Device layout for gate last process

Chemical mechanical polishing (CMP) method for gate last process

3-dimensional device design layout

CHUNG SHENG-CHEN

Resistive device for high-k metal gate technology

Method for N/P patterning in a gate last process

Device scheme of HKMG gate-last process

YEH CHIUNG-HAN

Method for tuning a work function of high-K metal gate devices

Integrating a first contact structure in a gate last process

THEI KONG-BENG

Fuse structure

Poly resistor and poly eFuse design for replacement gate technology

LAW OSCAR M K

Standard cell architecture and methods with variable design rules

Low leakage capacitors including portions in inter-layer dielectrics

CHEN CHIEN-HAO

Method of fabricating a sealing structure for high-k metal gate

Sealing structure for high-K metal gate

HSU CHEN-PIN

Downsize polysilicon height for polysilicon resistor integration of replacement gate process

Method of fabricating spacers in a strained semiconductor device

TSAI HUNG CHIH

Method for removing hard masks on gates in semiconductor manufacturing process