Inventor
GILES MARTIN D
US28 patents
⚠️ This page may combine multiple inventors who share the name “GILES MARTIN D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
15 patentsUS6982433B2Jan 3, 2006
Gate-induced strain for MOS performance improvement
INTEL CORP69 citations98
US9595581B2Mar 14, 2017
Silicon and silicon germanium nanowire structures
INTEL CORP7 citations84
US7470972B2Dec 30, 2008
Complementary metal oxide semiconductor integrated circuit using uniaxial compressive stress and biaxial compressive stress
INTEL CORP15 citations82
US7452764B2Nov 18, 2008
Gate-induced strain for MOS performance improvement
INTEL CORP5 citations74
US10985184B2Apr 20, 2021
Fins for metal oxide semiconductor device structures
INTEL CORP2 citations73
US12205955B2Jan 21, 2025
Fins for metal oxide semiconductor device structures
INTEL CORP0 citations62
US7473614B2Jan 6, 2009
Method for manufacturing a silicon-on-insulator (SOI) wafer with an etch stop layer
INTEL CORP6 citations62
US7679145B2Mar 16, 2010
Transistor performance enhancement using engineered strains
INTEL CORP5 citations61
US7091560B2Aug 15, 2006
Method and structure to decrease area capacitance within a buried insulator device
INTEL CORP2 citations61
US6867104B2Mar 15, 2005
Method to form a structure to decrease area capacitance within a buried insulator device
INTEL CORP2 citations61
US10847653B2Nov 24, 2020
Semiconductor device having metallic source and drain regions
INTEL CORP0 citations52
US10636871B2Apr 28, 2020
Silicon and silicon germanium nanowire structures
INTEL CORP0 citations52
US10580899B2Mar 3, 2020
Nanowire structures having non-discrete source and drain regions
INTEL CORP0 citations52
US9680013B2Jun 13, 2017
Non-planar device having uniaxially strained semiconductor body and method of making same
INTEL CORP0 citations52
US7719057B2May 18, 2010
Multiple oxide thickness for a semiconductor device
INTEL CORP0 citations42
CEA STEPHEN M
5 patentsUS8558279B2Oct 15, 2013
Non-planar device having uniaxially strained semiconductor body and method of making same
CEA STEPHEN M15 citations92
US8269283B2Sep 18, 2012
Methods and apparatus to reduce layout based strain variations in non-planar transistor structures
CEA STEPHEN M18 citations92
US9564522B2Feb 7, 2017
Nanowire structures having non-discrete source and drain regions
CEA STEPHEN M6 citations84
US9087863B2Jul 21, 2015
Nanowire structures having non-discrete source and drain regions
CEA STEPHEN M10 citations84
US8487348B2Jul 16, 2013
Methods and apparatus to reduce layout based strain variations in non-planar transistor structures
CEA STEPHEN M8 citations83