P

Inventor

NAIR DELEEP R

US12 patents
⚠️ This page may combine multiple inventors who share the name “NAIR DELEEP R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IBM

3 patents
US9196707B2Nov 24, 2015

Oxygen scavenging spacer for a gate electrode

IBM4 citations72
US7863112B2Jan 4, 2011

Method and structure to protect FETs from plasma damage during FEOL processing

IBM5 citations62
US7521308B2Apr 21, 2009

Dual layer stress liner for MOSFETS

IBM3 citations61

CHEN XIANGDONG

2 patents
US8298897B2Oct 30, 2012

Asymmetric channel MOSFET

CHEN XIANGDONG8 citations83
US8237197B2Aug 7, 2012

Asymmetric channel MOSFET

CHEN XIANGDONG7 citations83

CHUDZIK MICHAEL P

1 patent
US9059211B2Jun 16, 2015

Oxygen scavenging spacer for a gate electrode

CHUDZIK MICHAEL P4 citations72

KANIKE NARASIMHULU

1 patent
US8993402B2Mar 31, 2015

Method of manufacturing a body-contacted SOI FINFET

KANIKE NARASIMHULU6 citations71

BAIOCCO CHRISTOPHER VINCENT

1 patent
US9093495B2Jul 28, 2015

Method and structure to reduce FET threshold voltage shift due to oxygen diffusion

BAIOCCO CHRISTOPHER VINCENT4 citations64

LI WEIPENG

1 patent
US8563394B2Oct 22, 2013

Integrated circuit structure having substantially planar N-P step height and methods of forming

LI WEIPENG2 citations60

GLOBALFOUNDRIES INC

1 patent
US9431289B2Aug 30, 2016

Method and structure to reduce FET threshold voltage shift due to oxygen diffusion

GLOBALFOUNDRIES INC0 citations50

PARK JAE-EUN

1 patent
US8623714B2Jan 7, 2014

Spacer protection and electrical connection for array device

PARK JAE-EUN1 citations45

TEH YOUNG WAY

1 patent
US8853796B2Oct 7, 2014

High-K metal gate device

TEH YOUNG WAY1 citations40