Inventor
PHILLIPS JOEL R
US20 patents
⚠️ This page may combine multiple inventors who share the name “PHILLIPS JOEL R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
CADENCE DESIGN SYSTEMS INC
10 patentsUS7882471B1Feb 1, 2011
Timing and signal integrity analysis of integrated circuits with semiconductor process variations
CADENCE DESIGN SYSTEMS INC56 citations97
US7428477B1Sep 23, 2008
Simulation of electrical circuits
CADENCE DESIGN SYSTEMS INC20 citations91
US8966421B1Feb 24, 2015
Static timing analysis methods for integrated circuit designs using a multi-CCC current source model
CADENCE DESIGN SYSTEMS INC8 citations84
US7590518B2Sep 15, 2009
Circuit analysis utilizing rank revealing factorization
CADENCE DESIGN SYSTEMS INC11 citations84
US7533359B2May 12, 2009
Method and system for chip design using physically appropriate component models and extraction
CADENCE DESIGN SYSTEMS INC17 citations84
US8375343B1Feb 12, 2013
Methods and apparatus for waveform based variational static timing analysis
CADENCE DESIGN SYSTEMS INC8 citations83
US7487078B1Feb 3, 2009
Method and system for modeling distributed time invariant systems
CADENCE DESIGN SYSTEMS INC15 citations82
US8726211B2May 13, 2014
Generating an equivalent waveform model in static timing analysis
CADENCE DESIGN SYSTEMS INC8 citations81
US7493240B1Feb 17, 2009
Method and apparatus for simulating quasi-periodic circuit operating conditions using a mixed frequency/time algorithm
CADENCE DESIGN SYSTEMS INC13 citations81
US10860767B1Dec 8, 2020
Systems and methods for transient simulation of circuits with mutual inductors
CADENCE DESIGN SYSTEMS INC7 citations78
TIWARY SAURABH K
4 patentsUS8245165B1Aug 14, 2012
Methods and apparatus for waveform based variational static timing analysis
TIWARY SAURABH K36 citations94
US8341572B1Dec 25, 2012
Methods and apparatus for waveform based variational static timing analysis
TIWARY SAURABH K17 citations91
US8782583B1Jul 15, 2014
Waveform based variational static timing analysis
TIWARY SAURABH K7 citations82
US8341567B1Dec 25, 2012
Boolean satisfiability based verification of analog circuits
TIWARY SAURABH K7 citations79
KARIAT VINOD
3 patentsUS8516420B1Aug 20, 2013
Sensitivity and static timing analysis for integrated circuit designs using a multi-CCC current source model
KARIAT VINOD19 citations92
US8631369B1Jan 14, 2014
Methods, systems, and apparatus for timing and signal integrity analysis of integrated circuits with semiconductor process variations
KARIAT VINOD10 citations83
US8533644B1Sep 10, 2013
Multi-CCC current source models and static timing analysis methods for integrated circuit designs
KARIAT VINOD3 citations62