Inventor
HANDLOGTEN GLEN HOWARD
US22 patents
⚠️ This page may combine multiple inventors who share the name “HANDLOGTEN GLEN HOWARD”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
21 patentsUS7046676B2May 16, 2006
QoS scheduler and method for implementing quality of service with cached status array
IBM25 citations92
US6987760B2Jan 17, 2006
High speed network processor
IBM31 citations92
US5943249AAug 24, 1999
Method and apparatus to perform pipelined denormalization of floating-point results
IBM44 citations92
US7317683B2Jan 8, 2008
Weighted fair queue serving plural output ports
IBM11 citations83
US7187684B2Mar 6, 2007
Weighted fair queue having extended effective range
IBM11 citations83
US6684232B1Jan 27, 2004
Method and predictor for streamlining execution of convert-to-integer operations
IBM15 citations82
US7257124B2Aug 14, 2007
Method and apparatus for improving the fairness of new attaches to a weighted fair queue in a quality of service (QoS) scheduler
IBM7 citations73
US7103051B2Sep 5, 2006
QoS scheduler and method for implementing quality of service with aging time stamps
IBM7 citations73
US6982986B2Jan 3, 2006
QoS scheduler and method for implementing quality of service anticipating the end of a chain of flows
IBM10 citations73
US6973036B2Dec 6, 2005
QoS scheduler and method for implementing peak service distance using next peak service time violated indication
IBM11 citations73
US7362706B2Apr 22, 2008
Method and apparatus for hierarchial scheduling of virtual paths with underutilized bandwidth
IBM7 citations72
US7929548B2Apr 19, 2011
Weighted fair queue serving plural output ports
IBM2 citations62
US7680043B2Mar 16, 2010
Network processor having fast flow queue disable process
IBM3 citations62
US7543204B2Jun 2, 2009
Method, apparatus and computer program product for designing logic scan chains for matching gated portions of a clock tree
IBM4 citations62
US7509611B2Mar 24, 2009
Heuristic clustering of circuit elements in a circuit design
IBM5 citations62
US7398505B2Jul 8, 2008
Automatic back annotation of a functional definition of an integrated circuit design based upon physical layout
IBM2 citations62
US7280474B2Oct 9, 2007
Weighted fair queue having adjustable scaling factor
IBM5 citations62
US7660251B2Feb 9, 2010
Method and apparatus for hierarchial scheduling of virtual paths with underutilized bandwidth
IBM5 citations61
US7310345B2Dec 18, 2007
Empty indicators for weighted fair queues
IBM4 citations61
US7130270B2Oct 31, 2006
Method and apparatus for varying bandwidth provided to virtual channels in a virtual path
IBM5 citations61
US7231479B2Jun 12, 2007
Round robin selection logic improves area efficiency and circuit speed
IBM0 citations42