Inventor
MCBRIDE CHAD B
US23 patents
⚠️ This page may combine multiple inventors who share the name “MCBRIDE CHAD B”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
18 patentsUS6836767B2Dec 28, 2004
Pipelined hardware implementation of a neural network circuit
IBM27 citations92
US6453366B1Sep 17, 2002
Method and apparatus for direct memory access (DMA) with dataflow blocking for users
IBM17 citations83
US6289430B1Sep 11, 2001
Method and apparatus for target addressing and translation in a non-uniform memory environment with user defined target tags
IBM11 citations72
US6011412AJan 4, 2000
Frequency shift detection circuit with selectable granularity
IBM13 citations72
US5977837ANov 2, 1999
Phase selector for external frequency divider and phase locked loop
IBM13 citations72
US6601122B1Jul 29, 2003
Exceptions and interrupts with dynamic priority and vector routing
IBM12 citations70
US7917700B2Mar 29, 2011
Method and cache control circuit for replacing cache lines using alternate PLRU algorithm and victim cache coherency state
IBM2 citations62
US7716423B2May 11, 2010
Pseudo LRU algorithm for hint-locking during software and hardware address translation cache miss handling modes
IBM5 citations62
US7634591B2Dec 15, 2009
Method and apparatus for tracking command order dependencies
IBM4 citations62
US7543204B2Jun 2, 2009
Method, apparatus and computer program product for designing logic scan chains for matching gated portions of a clock tree
IBM4 citations62
US7509611B2Mar 24, 2009
Heuristic clustering of circuit elements in a circuit design
IBM5 citations62
US7430699B2Sep 30, 2008
Trading propensity-based clustering of circuit elements in a circuit design
IBM2 citations62
US7398505B2Jul 8, 2008
Automatic back annotation of a functional definition of an integrated circuit design based upon physical layout
IBM2 citations62
US7149218B2Dec 12, 2006
Cache line cut through of limited life data in a data processing system
IBM3 citations59
US7472227B2Dec 30, 2008
Invalidating multiple address cache entries
IBM1 citations51
US7330479B2Feb 12, 2008
Shared transmit buffer for network processor and methods for using same
IBM1 citations51
US9405315B2Aug 2, 2016
Delayed execution of program code on multiple processors
IBM0 citations50
US7539840B2May 26, 2009
Handling concurrent address translation cache misses and hits under those misses while maintaining command order
IBM1 citations47