Inventor
MOON PETER K
US25 patents
⚠️ This page may combine multiple inventors who share the name “MOON PETER K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
23 patentsUS7018918B2Mar 28, 2006
Method of forming a selectively converted inter-layer dielectric using a porogen material
INTEL CORP76 citations97
US5719085AFeb 17, 1998
Shallow trench isolation technique
INTEL CORP513 citations97
US5985735ANov 16, 1999
Trench isolation process using nitrogen preconditioning to reduce crystal defects
INTEL CORP49 citations93
US7586196B2Sep 8, 2009
Apparatus for an improved air gap interconnect structure
INTEL CORP16 citations92
US6943121B2Sep 13, 2005
Selectively converted inter-layer dielectric
INTEL CORP43 citations92
US6878465B2Apr 12, 2005
Under bump metallurgy for Lead-Tin bump over copper pad
INTEL CORP19 citations92
US6703069B1Mar 9, 2004
Under bump metallurgy for lead-tin bump over copper pad
INTEL CORP33 citations92
US6118168ASep 12, 2000
Trench isolation process using nitrogen preconditioning to reduce crystal defects
INTEL CORP29 citations90
US6649515B2Nov 18, 2003
Photoimageable material patterning techniques useful in fabricating conductive lines in circuit structures
INTEL CORP35 citations89
US7304388B2Dec 4, 2007
Method and apparatus for an improved air gap interconnect structure
INTEL CORP10 citations84
US6833320B2Dec 21, 2004
Removing sacrificial material by thermal decomposition
INTEL CORP14 citations84
US5911111AJun 8, 1999
Polysilicon polish for patterning improvement
INTEL CORP18 citations84
US7402519B2Jul 22, 2008
Interconnects having sealing structures to enable selective metal capping layers
INTEL CORP6 citations74
US7060617B2Jun 13, 2006
Method of protecting a seed layer for electroplating
INTEL CORP5 citations74
US9437545B2Sep 6, 2016
Interconnects having sealing structures to enable selective metal capping layers
INTEL CORP1 citations63
US7223694B2May 29, 2007
Method for improving selectivity of electroless metal deposition
INTEL CORP4 citations63
US7239019B2Jul 3, 2007
Selectively converted inter-layer dielectric
INTEL CORP2 citations62
US7078754B2Jul 18, 2006
Methods and apparatuses for producing a polymer memory device
INTEL CORP4 citations62
US6900063B2May 31, 2005
Methods and apparatuses for producing a polymer memory device
INTEL CORP2 citations62
US9984922B2May 29, 2018
Interconnects having sealing structures to enable selective metal capping layers
INTEL CORP0 citations52
US7629268B2Dec 8, 2009
Method for an improved air gap interconnect structure
INTEL CORP0 citations52
US7525196B2Apr 28, 2009
Protection of seedlayer for electroplating
INTEL CORP0 citations52
US7326981B2Feb 5, 2008
Methods and apparatuses for producing a polymer memory device
INTEL CORP0 citations51