Inventor
RADIN GEORGE
US7 patents
Patents
7 patentsUSRE37305EJul 31, 2001
Virtual memory address translation mechanism with controlled data persistence
IBM95 citations97
US4569016AFeb 4, 1986
Mechanism for implementing one machine cycle executable mask and rotate instructions in a primitive instruction set computing system
IBM200 citations97
US4638426AJan 20, 1987
Virtual memory address translation mechanism with controlled data persistence
IBM106 citations95
US4589087AMay 13, 1986
Condition register architecture for a primitive instruction set machine
IBM59 citations95
US4589065AMay 13, 1986
Mechanism for implementing one machine cycle executable trap instructions in a primitive instruction set computing system
IBM46 citations91
US4587612AMay 6, 1986
Accelerated instruction mapping external to source and target instruction streams for near realtime injection into the latter
IBM100 citations91
US4947316AAug 7, 1990
Internal bus architecture employing a simplified rapidly executable instruction set
IBM30 citations87