Inventor
CRISENZA GIUSEPPE
IT14 patents
⚠️ This page may combine multiple inventors who share the name “CRISENZA GIUSEPPE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
SGS THOMSON MICROELECTRONICS
6 patentsUS5717636AFeb 10, 1998
EEPROM memory with contactless memory cells
SGS THOMSON MICROELECTRONICS85 citations96
US6187683B1Feb 13, 2001
Method for final passivation of integrated circuit
SGS THOMSON MICROELECTRONICS28 citations91
US5543633AAug 6, 1996
Process and structure for measuring the planarity degree of a dielectric layer in an integrated circuit and integrated circuit including means for performing said process
SGS THOMSON MICROELECTRONICS19 citations91
US5798279AAug 25, 1998
Method of fabricating non-volatile memories with overlapping layers
SGS THOMSON MICROELECTRONICS17 citations83
US5568418AOct 22, 1996
Non-volatile memory in an integrated circuit
SGS THOMSON MICROELECTRONICS14 citations73
US6087729AJul 11, 2000
Low dielectric constant composite film for integrated circuits of an inorganic aerogel and an organic filler grafted to the inorganic material
SGS THOMSON MICROELECTRONICS14 citations72
ST MICROELECTRONICS SRL
6 patentsUS5633822AMay 27, 1997
Method of programming a nonvolatile flash-EEPROM memory array using source line switching transistors
ST MICROELECTRONICS SRL34 citations92
US5587946ADec 24, 1996
Method of reading, erasing and programming a nonvolatile flash-EEPROM memory arrray using source line switching transistors
ST MICROELECTRONICS SRL17 citations82
US5464784ANov 7, 1995
Method of fabricating integrated devices
ST MICROELECTRONICS SRL17 citations81
US5508956AApr 16, 1996
Nonvolatile flash-EEPROM memory array with source control transistors
ST MICROELECTRONICS SRL12 citations74
US6067250AMay 23, 2000
Method and apparatus for localizing point defects causing leakage currents in a non-volatile memory device
ST MICROELECTRONICS SRL8 citations73
US5977586ANov 2, 1999
Non-volatile integrated low-doped drain device with partially overlapping gate regions
ST MICROELECTRONICS SRL11 citations73
SGS MICROELETTRONICA SPA
2 patentsUS4808261AFeb 28, 1989
Fabrication process for EPROM cells with oxide-nitride-oxide dielectric
SGS MICROELETTRONICA SPA27 citations92
US4719184AJan 12, 1988
Process for the fabrication of integrated structures including nonvolatile memory cells with layers of self-aligned silicon and associated transistors
SGS MICROELETTRONICA SPA17 citations70