Inventor
EPPS GARRY P
US22 patents
⚠️ This page may combine multiple inventors who share the name “EPPS GARRY P”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
CISCO TECH INC
13 patentsUS7643486B2Jan 5, 2010
Pipelined packet switching and queuing architecture
CISCO TECH INC86 citations97
US7177276B1Feb 13, 2007
Pipelined packet switching and queuing architecture
CISCO TECH INC88 citations97
US7792027B2Sep 7, 2010
Pipelined packet switching and queuing architecture
CISCO TECH INC30 citations95
US7715419B2May 11, 2010
Pipelined packet switching and queuing architecture
CISCO TECH INC45 citations95
US8018937B2Sep 13, 2011
Pipelined packet switching and queuing architecture
CISCO TECH INC21 citations92
US7864791B2Jan 4, 2011
Pipelined packet switching and queuing architecture
CISCO TECH INC20 citations92
US7809009B2Oct 5, 2010
Pipelined packet switching and queuing architecture
CISCO TECH INC26 citations92
US7729351B2Jun 1, 2010
Pipelined packet switching and queuing architecture
CISCO TECH INC13 citations92
US7554907B1Jun 30, 2009
High-speed hardware implementation of RED congestion control algorithm
CISCO TECH INC24 citations92
US7310695B2Dec 18, 2007
Port adapter for high-bandwidth bus
CISCO TECH INC14 citations92
US7111102B2Sep 19, 2006
Port adapter for high-bandwidth bus
CISCO TECH INC26 citations90
US7286525B1Oct 23, 2007
Synchronous pipelined switch using serial transmission
CISCO TECH INC10 citations84
US7433988B2Oct 7, 2008
Port adapter for high-bandwidth bus
CISCO TECH INC4 citations60
CISCO TECH IND
7 patentsUS6977930B1Dec 20, 2005
Pipelined packet switching and queuing architecture
CISCO TECH IND193 citations99
US6813243B1Nov 2, 2004
High-speed hardware implementation of red congestion control algorithm
CISCO TECH IND142 citations99
US6778546B1Aug 17, 2004
High-speed hardware implementation of MDRR algorithm over a large number of queues
CISCO TECH IND169 citations99
US6721316B1Apr 13, 2004
Flexible engine and data structure for packet header processing
CISCO TECH IND207 citations99
US6731644B1May 4, 2004
Flexible DMA engine for packet header modification
CISCO TECH IND99 citations98
US6980552B1Dec 27, 2005
Pipelined packet switching and queuing architecture
CISCO TECH IND196 citations97
US6424649B1Jul 23, 2002
Synchronous pipelined switch using serial transmission
CISCO TECH IND35 citations92