Inventor

HOOKER RODNEY E

US130 patents

⚠️ This page may combine multiple inventors who share the name “HOOKER RODNEY E”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HOOKER RODNEY E

IP FIRST LLC

Microprocessor with repeat prefetch instruction

Translation lookaside buffer that caches memory type information

Compare branch instruction pairing within a single integer pipeline

Pairing of load-ALU-store with conditional branch

Apparatus and method for extending a microprocessor instruction set

Mechanism for extending the number of registers in a microprocessor

Apparatus and method for selective memory attribute control

Apparatus and method for extending a microprocessor instruction set

Microprocessor and method for utilizing disparity between bus clock and core clock frequencies to prioritize cache line fill bus access requests

Microprocessor and method for performing selective prefetch based on bus activity level

Virtual set cache that redirects store data to correct virtual set to avoid virtual set store miss penalty

Apparatus and method for speculatively forwarding storehit data based on physical page index compare

Byte-wise tracking on write allocate

Method and apparatus for speculative microinstruction pairing

Store-induced instruction coherency mechanism

Apparatus and method for selective control of condition code write back

Apparatus and method for conditional instruction execution

Microprocessor and apparatus for performing speculative load operation from a stack memory cache

Microprocessor, apparatus and method for selective prefetch retire

Apparatus and method for extending data modes in a microprocessor

Microprocessor and apparatus for performing fast speculative pop operation from a stack memory cache

Microprocessor apparatus and method for prefetch, allocation, and initialization of a cache line from memory

Write back and invalidate mechanism for multiple cache lines

Method and apparatus for store forwarding using a response buffer data path in a write-allocate-configurable microprocessor

Apparatus and method for performing write-combining in a pipelined microprocessor using tags

VIA TECH INC

Processor that performs approximate computing instructions

Apparatus and method for instruction-level specification of floating point format

Microprocessor with repeat prefetch indirect instruction

Apparatus and method for performing a detached load operation in a pipeline microprocessor

Inter-core communication via uncore RAM

Bounding box prefetcher

Microprocessor with private microcode RAM

Asymmetric multi-core processor with native switching mechanism

VIA ALLIANCE SEMICONDUCTOR CO LTD

Set associative cache memory with heterogeneous replacement policy

Sanitize-aware DRAM controller

Fractional use of prediction history storage for operating system routines

Prefetching with level of aggressiveness based on effectiveness by memory access type

Compiler system for a processor with an expandable instruction set architecture for dynamically configuring execution resources

HENRY G GLENN

Accessing model specific registers (MSR) with different sets of distinct microinstructions for instructions of different instruction set architecture (ISA)

Microprocessor that translates conditional load/store instructions into variable number of microinstructions

Guaranteed prefetch instruction

Fast REP STOS using grabline operations

COL GERARD M

Microprocessor with fused store address/store data microinstruction

Microprocessor with ALU integrated into load unit

DAY MATTHEW DANIEL

Out-of-order execution microprocessor with reduced store collision load replay by making an issuing of a load instruction dependent upon a dependee instruction of a store instruction

Out-of-order execution microprocessor with reduced store collision load replay reduction

I P FIRST LLC

Method and apparatus for resolving additional load misses and page table walks under orthogonal stalls in a single pipeline processor

EDDY COLIN

Microprocessor cache line evict array

HOOKER RODNEY E

Bounding box prefetcher

GLOVER CLINTON THOMAS

Efficient data prefetching in the presence of load hits