Inventor

MASLEID ROBERT P

US100 patents

⚠️ This page may combine multiple inventors who share the name “MASLEID ROBERT P”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MASLEID ROBERT P

FUJITSU LTD

Complement reset multiplexer latch

Complement reset latch

Low latency clock distribution

FET circuit block with reduced self-heating

Hybrid bulk/silicon-on-insulator multiprocessors

Complement reset buffer

Cold clock power reduction

Four-state switched decoupling capacitor system for active power stabilizer

Optimal inductor management

Cold clock power reduction

FET circuit block with reduced self-heating

MASLEID ROBERT P

Cross point switch

Inverting zipper repeater circuit

Low RC global clock distribution

Multi-write memory circuit with a data input and a clock input

Transit state element

Deep well regions for routing body-bias voltage to mosfets in surface well regions having separation wells of p-type between the segmented deep n wells

Micro-link high-bandwidth chip-to-chip bus

Dynamic ring oscillators

IBM

Independent clock edge regulation

Split drive clock buffer

Conditional recharge for dynamic logic

Method of making bit stack compatible input/output circuits

Pass gate multiplexer receiver circuit

Electronically tuneable computer clocking system and method of electronically tuning distribution lines of a computer clocking system

Bit stack compatible input/output circuits

Minimal recharge overhead circuit for domino SRAM structures

TRANSMETA CORP

Stacked inverter delay chain

Circuits, systems and methods relating to dynamic ring oscillators

Inverting zipper repeater circuit

Structure for spanning gap in body-bias voltage routing structure

Triple latch flip flop system and method

Column select multiplexer circuit for a domino random access memory array

ORACLE INT CORP

Level shifter circuit optimized for metastability resolution and integrated level shifter and metastability resolution circuit

Decoder circuit with reduced current leakage

Rotational synchronizer circuit for metastablity resolution

Multiple on-die communication networks

Variable run length encoding of a bit stream

LE HANH-PHUC

Delay chain initialization

Precision sampling circuit

Minimal bubble voltage regulator

INTELLECTUAL VENTURES HOLDING 81 LLC

Body-bias voltage routing structures

Body-bias voltage routing structures

ORACLE AMERICA INC

Latch with clocked devices

Integrated clock and power distribution

GROSS KENNY C

Near-isotropic antenna for monitoring electromagnetic signals

KAPIL SANJIV

Method and apparatus for modulating the width of a high-speed link

SMITH ALAN P

Flop type selection for very large scale integrated circuits

GREENHILL DAVID J

Power-supply noise suppression using a frequency-locked loop

ROZAS GUILLERMO

Dual ported replicated data cache