Inventor
UHLER G MICHAEL
US29 patents
⚠️ This page may combine multiple inventors who share the name “UHLER G MICHAEL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
MIPS TECH INC
18 patentsUS7185183B1Feb 27, 2007
Atomic update of CPO state
MIPS TECH INC96 citations98
US7181600B1Feb 20, 2007
Read-only access to CPO registers
MIPS TECH INC73 citations98
US6681283B1Jan 20, 2004
Coherent data apparatus for an on-chip split transaction system bus
MIPS TECH INC77 citations98
US6490642B1Dec 3, 2002
Locked read/write on separate address/data bus using write barrier
MIPS TECH INC80 citations98
US7242414B1Jul 10, 2007
Processor having a compare extension of an instruction set architecture
MIPS TECH INC71 citations97
US6493776B1Dec 10, 2002
Scalable on-chip system bus
MIPS TECH INC95 citations97
US6604159B1Aug 5, 2003
Data release to reduce latency in on-chip system bus
MIPS TECH INC36 citations93
US7853777B2Dec 14, 2010
Instruction/skid buffers in a multithreading microprocessor that store dispatched instructions to avoid re-fetching flushed instructions
MIPS TECH INC43 citations92
US6732259B1May 4, 2004
Processor having a conditional branch extension of an instruction set architecture
MIPS TECH INC32 citations92
US6714197B1Mar 30, 2004
Processor having an arithmetic extension of an instruction set architecture
MIPS TECH INC45 citations92
US6651156B1Nov 18, 2003
Mechanism for extending properties of virtual memory pages by a TLB
MIPS TECH INC40 citations92
US7724261B2May 25, 2010
Processor having a compare extension of an instruction set architecture
MIPS TECH INC13 citations84
US7487339B2Feb 3, 2009
Method and apparatus for binding shadow registers to vectored interrupts
MIPS TECH INC9 citations84
US7065675B1Jun 20, 2006
System and method for speeding up EJTAG block data transfers
MIPS TECH INC11 citations82
US7487332B2Feb 3, 2009
Method and apparatus for binding shadow registers to vectored interrupts
MIPS TECH INC5 citations74
US7925864B2Apr 12, 2011
Method and apparatus for binding shadow registers to vectored interrupts
MIPS TECH INC2 citations63
US7552261B2Jun 23, 2009
Configurable prioritization of core generated interrupts
MIPS TECH INC5 citations63
US7000095B2Feb 14, 2006
Method and apparatus for clearing hazards using jump instructions
MIPS TECH INC3 citations58
DIGITAL EQUIPMENT CORP
9 patentsUS5802272ASep 1, 1998
Method and apparatus for tracing unpredictable execution flows in a trace buffer of a high-speed computer system
DIGITAL EQUIPMENT CORP116 citations96
US5764885AJun 9, 1998
Apparatus and method for tracing data flows in high-speed computer systems
DIGITAL EQUIPMENT CORP108 citations96
US5481689AJan 2, 1996
Conversion of internal processor register commands to I/O space addresses
DIGITAL EQUIPMENT CORP95 citations96
US5450349ASep 12, 1995
Computer system performance evaluation system and method
DIGITAL EQUIPMENT CORP66 citations96
US5119483AJun 2, 1992
Application of state silos for recovery from memory management exceptions
DIGITAL EQUIPMENT CORP85 citations95
US5058006AOct 15, 1991
Method and apparatus for filtering invalidate requests
DIGITAL EQUIPMENT CORP86 citations95
US5579504ANov 26, 1996
Multi-processor computer system having shared memory, private cache memories, and invalidate queues having valid bits and flush bits for serializing transactions
DIGITAL EQUIPMENT CORP58 citations94
US5542058AJul 30, 1996
Pipelined computer with operand context queue to simplify context-dependent execution flow
DIGITAL EQUIPMENT CORP66 citations94
US4851991AJul 25, 1989
Central processor unit for digital data processing system including write buffer management mechanism
DIGITAL EQUIPMENT CORP33 citations90