Inventor

EDDY COLIN

US75 patents

⚠️ This page may combine multiple inventors who share the name “EDDY COLIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

EDDY COLIN

VIA ALLIANCE SEMICONDUCTOR CO LTD

Set associative cache memory with heterogeneous replacement policy

Simultaneous invalidation of all address translation cache entries associated with an X86 process context identifier

Address translation cache that supports simultaneous invalidation of common context entries

Prefetching with level of aggressiveness based on effectiveness by memory access type

Programmable load replay precluding mechanism

Cache memory budgeted by ways based on memory access type

Processor including single invalidate page instruction

Multiple data prefetchers that defer to one another based on prefetch effectiveness by memory access type

Fully associative cache memory budgeted by memory access type

Cache replacement policy that considers memory access type

System and method for performing hardware prefetch tablewalks having lowest tablewalk priority

Cache system with a primary cache and an overflow cache that use different indexing schemes

Mechanism to preclude uncacheable-dependent load replays in out-of-order processor

Power saving mechanism to reduce load replays in out-of-order processor

Cache memory budgeted by chunks based on memory access type

System and method of determining memory ownership on cache line basis for detecting self-modifying code including code with looping instructions

System and method of determining memory ownership on cache line basis for detecting self-modifying code

System and method of determining memory ownership on cache line basis for detecting self-modifying code including modification of a cache line with an executing instruction

Processor including load EPT instruction

System and method of determining memory ownership on cache line basis for detecting self-modifying code including code with instruction that overlaps cache line boundaries

Power saving mechanism to reduce load replays in out-of-order processor

Efficient address translation caching in a processor that supports a large number of different address spaces

Apparatus and method for programmable load replay preclusion

Apparatus and method for programmable load replay preclusion

Apparatus and method to preclude non-core cache-dependent load replays in an out-of-order processor

Apparatus and method to preclude load replays dependent on write combining memory space access in an out-of-order processor

Apparatus and method to preclude non-core cache-dependent load replays in an out-of-order processor

HENRY G GLENN

Microprocessor that translates conditional load/store instructions into variable number of microinstructions

Guaranteed prefetch instruction

Fast REP STOS using grabline operations

Conditional load instructions in an out-of-order execution microprocessor

Conditional store instructions in an out-of-order execution microprocessor

HOOKER RODNEY E

Store-to-load forwarding based on load/store address computation source information comparisons

Microprocessor with multiple operating modes dynamically configurable by a device driver based on currently running applications

Prefetching of next physically sequential cache line after cache line that includes loaded page table entry

Multi-modal data prefetcher

EDDY COLIN

Microprocessor cache line evict array

Prefetching of next physically sequential cache line after cache line that includes loaded page table entry

Efficient pseudo-LRU for colliding accesses

VIA TECH INC

Microprocessor with private microcode RAM

Selective prefetching of physically sequential cache line to cache line that includes loaded page table entry

Microprocessor that performs speculative tablewalks

GLOVER CLINTON THOMAS

Efficient data prefetching in the presence of load hits

Efficient data prefetching in the presence of load hits

Efficient data prefetching in the presence of load hits

COL GERARD M

Microprocessor with ALU integrated into load unit

Microprocessor with ALU integrated into store unit

CENTAUR TECH INC

L1D to L2 eviction

Tablewalk takeover

POGOR BRYAN WAYNE

Microprocessor that performs a two-pass breakpoint check for a cache line-crossing load/store operation