Inventor
CHENEY LANCE
US12 patents
⚠️ This page may combine multiple inventors who share the name “CHENEY LANCE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
11 patentsUS10803548B2Oct 13, 2020
Disaggregation of SOC architecture
INTEL CORP32 citations97
US11756150B2Sep 12, 2023
Disaggregation of system-on-chip (SOC) architecture
INTEL CORP5 citations85
US11410266B2Aug 9, 2022
Disaggregation of System-On-Chip (SOC) architecture
INTEL CORP6 citations85
US11386521B2Jul 12, 2022
Enabling product SKUS based on chiplet configurations
INTEL CORP2 citations72
US10909652B2Feb 2, 2021
Enabling product SKUs based on chiplet configurations
INTEL CORP4 citations72
US12141890B2Nov 12, 2024
Enabling product SKUs based on chiplet configurations
INTEL CORP0 citations62
US12112398B2Oct 8, 2024
Disaggregation of system-on-chip (SOC) architecture
INTEL CORP0 citations62
US12056789B2Aug 6, 2024
Disaggregation of system-on-chip (SOC) architecture
INTEL CORP0 citations62
US11763416B2Sep 19, 2023
Disaggregation of system-on-chip (SOC) architecture
INTEL CORP0 citations62
US7793187B2Sep 7, 2010
Checking output from multiple execution units
INTEL CORP5 citations61
US7904701B2Mar 8, 2011
Activating a design test mode in a graphics card having multiple execution units to bypass a host cache and transfer test instructions directly to an instruction cache
INTEL CORP2 citations60