Inventor

PILEGGI LAWRENCE

US16 patents

⚠️ This page may combine multiple inventors who share the name “PILEGGI LAWRENCE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

UNIV CARNEGIE MELLON

7 patents

US7634248B2Dec 15, 2009

MONTEREY DESIGN SYSTEMS INC

4 patents

US6286128B1Sep 4, 2001

Method for design optimization using logical and physical information

MONTEREY DESIGN SYSTEMS INC202 citations95

US6651232B1Nov 18, 2003

Method and system for progressive clock tree or mesh construction concurrently with physical design

MONTEREY DESIGN SYSTEMS INC35 citations91

US6367051B1Apr 2, 2002

System and method for concurrent buffer insertion and placement of logic gates

MONTEREY DESIGN SYSTEMS INC31 citations90

US6385760B2May 7, 2002

System and method for concurrent placement of gates and associated wiring

MONTEREY DESIGN SYSTEMS INC9 citations73

MONTEREY DESIGN SYSTEMS

3 patents

US6442743B1Aug 27, 2002

Placement method for integrated circuit design using topo-clustering

MONTEREY DESIGN SYSTEMS126 citations96

US6192508B1Feb 20, 2001

Method for logic optimization for improving timing and congestion during placement in integrated circuit design

MONTEREY DESIGN SYSTEMS23 citations91

US6449756B1Sep 10, 2002

Method for accurate and efficient updates of timing information logic synthesis, placement and routing for integrated circuit design

MONTEREY DESIGN SYSTEMS13 citations71

SYNOPSYS INC

1 patent

US6961916B2Nov 1, 2005

Placement method for integrated circuit design using topo-clustering

SYNOPSYS INC45 citations94

CELIK MUSTAFA

1 patent

US7487486B2Feb 3, 2009

Defining statistical sensitivity for timing optimization of logic circuits with large-scale process and environmental variations

CELIK MUSTAFA18 citations91

PILEGGI LAWRENCE

UNIV CARNEGIE MELLON

Configurable circuits using phase change switches

Optimization and design method for configurable analog circuits and devices

System and method to test integrated circuits on a wafer

Nonvolatile magnetic logic device

Magnetic shift register

Bitcell wth magnetic switching elements

Testing integrated circuits during split fabrication

MONTEREY DESIGN SYSTEMS INC

Method for design optimization using logical and physical information

Method and system for progressive clock tree or mesh construction concurrently with physical design

System and method for concurrent buffer insertion and placement of logic gates

System and method for concurrent placement of gates and associated wiring

MONTEREY DESIGN SYSTEMS

Placement method for integrated circuit design using topo-clustering

Method for logic optimization for improving timing and congestion during placement in integrated circuit design

Method for accurate and efficient updates of timing information logic synthesis, placement and routing for integrated circuit design

SYNOPSYS INC

Placement method for integrated circuit design using topo-clustering

CELIK MUSTAFA

Defining statistical sensitivity for timing optimization of logic circuits with large-scale process and environmental variations