Inventor

CHIDAMBARRAO DURESETI

US232 patents

⚠️ This page may combine multiple inventors who share the name “CHIDAMBARRAO DURESETI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHIDAMBARRAO DURESETI

IBM

Vertical Fin-FET MOS devices

Silicon device on Si:C-OI and SGOI and method of manufacture

Strained finFETs and method of manufacture

Structure and method to improve channel mobility by gate electrode stress modification

Structure and method of making strained semiconductor CMOS transistors having lattice-mismatched semiconductor regions underlying source and drain regions

Strained silicon NMOS devices with embedded source/drain

Stress inducing spacers

SOI based field effect transistor having a compressive film in undercut area under the channel and a method of making the device

Strained finFET CMOS device structures

Structure and method for improved stress and yield in pFETs with embedded SiGe source/drain regions

Isolation structures for imposing stress patterns

Channel MOSFET with strained silicon channel on strained SiGe

Process for producing metal interconnections and product produced thereby

Method of manufacture of FinFET devices with T-shaped fins and devices manufactured thereby

Pull-back method of forming fins in FinFets

Methodology for layout-based modulation and optimization of nitride liner stress effect in compact models

High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture

Structure and method for making strained channel field effect transistor using sacrificial spacer

MOSFET structure with high mechanical stress in the channel

Method and structure for improved MOSFETs using poly/silicide gate height control

MOSFET performance improvement using deformation in SOI structure

Silicide proximity structures for CMOS device performance improvements

Reduction of polysilicon stress in trench capacitors

Method of manufacturing an integrated ULSI heatsink

Integrated ULSI heatsink

Structure and method of making strained channel CMOS transistors having lattice-mismatched epitaxial extension and source and drain regions

Embedded silicon germanium using a double buried oxide silicon-on-insulator wafer

High performance strained silicon FinFETs device and method for forming same

Curved FINFETs

Embedded stressed nitride liners for CMOS performance improvement

Dual stressed SOI substrates

Strained Si on multiple materials for bulk or SOI substrates

Trench capacitor DRAM cell using buried oxide as array top oxide

Out of the box vertical transistor for eDRAM on SOI

Bipolar transistor with extrinsic stress layer

Method and structure for improved MOSFETs using poly/silicide gate height control

Dynamic threshold voltage MOSFET on SOI

Method of manufacturing strained dislocation-free channels for CMOS

Method of manufacturing a strained silicon on a SiGe on SOI substrate

Out of the box vertical transistor for eDRAM on SOI

Strained silicon on relaxed sige film with uniform misfit dislocation density

Trench capacitors with reduced polysilicon stress

Vertical DRAM punchthrough stop self-aligned to storage trench

Trench capacitor DRAM cell using buried oxide as array top oxide

Vertical DRAM punchthrough stop self-aligned to storage trench

Structure and method for improved vertical MOSFET DRAM cell-to-cell isolation

Self-aligned punch through stop for 6F2 rotated hybrid DRAM cell

LIU YAOCHENG

Structure and method for mobility enhanced MOSFETs with unalloyed silicide

Structure and method for mobility enhanced MOSFETS with unalloyed silicide

ZHU HUILONG

Semiconductor-on-insulator structures including a trench containing an insulator stressor plug and method of fabricating same